[1] Z. Zhang, Z. Zhu, X.

Zhang, Breaking Address Mapping Symmetry at Multi-levels of Memory Hierarchy to Reduce DRAM Row-buffer Conflicts, The Journal of Instruction-Level Parallelism, Vol. 3, 2002. [2] Z. Zhang, Z. Zhu, X. Zhang, A Permutation-based Page Interleaving Scheme to Reduce Row-buffer Conflicts and Exploit Data Locality, Proceedings of the 33rd IEEE/ACM International Symposium on Microarchitecture, Dec. 2000. pp32-41. [3] Z. Zhu, Z. Zhang, X. Zhang, "Fine-grain Priority Scheduling on Multi-channel Memory Systems". Proceedings of the 8th International Symposium on High Performance Computer Architecture (HPCA-8), Feb. 2002. [4] W. Lin, S. Reinhardt, D. Burger, Reducing DRAM Latencies with an Integrated Memory Hierarchy Design. 7th International Symposium on High-Performance Computer Architecture, January 2001. [5] V. Cuppu, B. Jacob, Organization Design Trade-offs at the DRAM, Memory Bus and Memory Controller Level: Initial Results, University of Maryland Systems and Computer Architecture Group Technical Report UMD-SCA-TR1999-2, Nov. 1999. [6] S. Rixner, W Dally, U. Kapasi, P. Mattson, J. Owens, Memory Access Scheduling, Proceedings of the 27th International Symposium on Computer Architecture, June 2000. [7] V. Cuppu, B. Jacob, "Concurrency, latency, or system overhead: Which has the largest impact on uniprocessor DRAM-system performance?", Proceedings of 28th International Symposium on Computer Architecture, June 2001 [8] S. McKee, "Dynamic Access Ordering: Bounds on Memory Bandwidth," Univ. of Virginia, Technical Report CS-9438, Oct. 1994. [9] M. Franklin, G. Sohi, ARB: A Hardware Mechanism for Dynamic Reordering of Memory References. IEEE Transactions on Computers. Vol. 45, No. 5, 1996. [10] S. Sair, M. Charney, Memory Behavior of the SPEC 2000 Benchmark Suite, IBM Research Report. October, 2000. [11] S. Hong, S. McKee, M. Salinas, R Klenke, J Aylor, W. Wulf, Access Order and Effective Bandwidth for Stream on a Direct Rambus Memory, The fifth International Symposium on High-Performance Computer Architecture. January 1999. [12] C. Zhang, S McKee, Hardware-Only Stream Prefetching and Dynamic Access Ordering, Proceedings of the 14th international conference on Supercomputing, 2000. [13] J. Alakarhu, A Comparison of Precharge Policies with Modern DRAM Architectures, Proceedings of the 9th International Conference on Eletronics, Circuits and Systems, Vol. 2, pp. 823-826, Sept 2002. [14] Z. Zhu, Z. Zhang, A Performance Comparison of DRAM Memory System Optimizations for SMT Processors, Proceedings of the 11th International Symposium on High-Performance Computer Architecture, February 2005. [15] S. Rixner, Memory Controller Optimizations for Web Servers, Proceedings of the 37th International Symposium on Microarchitecture. December 2004. [16] L. Zhang, Z. Fang, M. Parker, B. Mathew, L. Schaelicke, J. Carter, W. Hsieh, S. McKee, The Impulse Memory Controller, IEEE Transactions on Computers Vol. 50 , Issue 11, November 2001. [17] C. Natarajan, B. Christenson, F. Briggs, A Study of Performance Impact of Memory Controller Features in MultiProcessor Server Environment, Proceedings of the 3rd Workshop on Memory Performance Issues (WMPI-2004) [18] F. Briggs, M. Cekleov, K. Creta, M. Khare, S. Kulick, A. Kumar, L. Looi, C. Natarajan, S. Radhakrishnan, L. Rankin, Intel 870: A Building Block for Cost-Effective, Scalable Servers, IEEE Micro, ,Vol. 22, No. 2, March/April 2002

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