Microchip Technology Inc.

DS
Digital Signal Controller
Introduction to the dsPIC30F Architecture (Part 1 of 2)

2004 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC30F Architecture (Part 2)

Welcome to the second dsPIC30F web seminar: Introduction to the dsPIC30F Architecture, Part 1. The focus in todays seminar will be on the basics of the Central Processing Unit, or CPU, architecture, and the DSP elements of the dsPIC30F architecture.

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dsPIC30F CPU Architecture Overview

2004 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC30F Architecture (Part 2)

Let us begin by taking a closer look at the dsPIC30F CPU architecture.

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Architecture Highlights
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Single CPU integrating MCU & DSP functions Modified Harvard Bus Architecture: 3 operand instructions: A = B + C Extensive Addressing Modes 16 x 16-bit general purpose register set Fast, deterministic interrupt response Flexible software Stack with overflow detection

2004 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC30F Architecture (Part 2)

The dsPIC30F Central Processing Unit, or CPU, seamlessly integrates the best features of a 16-bit MCU and DSP. Single instruction thread execution simplifies application debug and ensures deterministic operation. The dsPIC30F architecture is a modified Harvard Bus Architecture. This means that the program and data memories are accessed by separate buses. However, there are mechanisms to store and access constant data from the program memory space. This enables more efficient use of the available on-chip memory for some applications. Some instructions, specifically the dual-operand DSP instructions, allow dual accesses from the data RAM during the same instruction cycle. This is of tremendous benefit for DSP applications such as signal filtering. The dsPIC30F provides a large number of addressing modes to ease code development and enhance C compiler efficiency. Most addressing modes operate orthogonally on a set of sixteen 16-bit general purpose registers, which means that by and large, all instructions support all addressing modes. Up to 45 individually vectored interrupt sources may be programmed to one of seven priority levels. Fixed five cycle latency, from Interrupt Request to Interrupt Service Routine entry, provides fast, deterministic application operation. The interrupt stack is part of the on-chip RAM, and provides automatic bound checking to prevent underflow or overflow.

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Basic Programmers Model

15 W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 0

DSP OPERAND Registers DSP ADDRESS Registers

W Registers General Purpose Data Registers or Address Pointers

Stack Pointer

DSP Accumulators (40-bit)

ACCA ACCB
39 22 32 31 16 15
0

15

Program Counter (23-bit) Status Register

DSP Status
2004 Microchip Technology Incorporated. All Rights Reserved.

MCU Status
4

Introduction to the dsPIC30F Architecture (Part 2)

The basic programmers model of the dsPIC30F is shown here. The dsPIC30F contains sixteen 16-bit general purpose working registers W0 through W15, which are collectively known as W registers. These registers may be used by the programmer for storing data or they may be used as address pointers. Moreover, the W registers are both byte and word accessible. Some of the W registers, besides being usable as general purpose registers, have some special functionality. For example, W15 is designated as the Stack Pointer to support interrupts or subroutine calls. W4 through W13 have some special roles to play when executing the MAC instruction. Some of the W registers are shadowed to provide a mechanism for fast context switching, for example, in a Real Time Operating System. Two 40-bit accumulators are provided primarily to support DSP operations, but could be just as useful for general-purpose MCU applications. The 23-bit program counter can linearly address up to 4 million instructions. Lastly, a 16-bit status register provides feedback on the state of the CPU, based on the result of various MCU and DSP operations.

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Program Memory Organization*

Interrupt Vector Table (0x000004 - 0x00007E)
Reset VectorGOTO instruction Interrupt Vector Table Reserved Alternate Vector Table 0x000000 0x000002 0x000004 0x00007E 0x000084

Executable code starts at 0x100

Program Instructions (0x000100 - 0x017FFE)
User Flash Program Memory (~48K Instructions)

0x0000FE 0x000100

Reserved Data EEPROM (4 K Bytes)

0x017FFE 0x018000 0x7FF000

0x800000 * Sample Program Memory Map shown here for dsPIC30F6014 device

Configuration Memory

Configuration Memory Space 0xFFFFFE

Introduction to the dsPIC30F Architecture (Part 2) 5

2004 Microchip Technology Incorporated. All Rights Reserved.

The Program Memory map of the dsPIC30F includes the reset vector, interrupt vector table, an alternate vector table, user Program Flash memory, Data EEPROM and configuration memory space. The Reset Vector is a 2 word GOTO instruction, and is therefore the only vector that occupies two words. All interrupt vector locations are filled with their respective interrupt service routine or ISR addresses, if an ISR is defined. There is an alternate vector table that can optionally be enabled by the user. It provides a complete set of all interrupt vectors, and is a useful aid during system debug. The executable 24-bit wide Program Flash memory starts at hex 100 in all dsPIC30F devices and progresses linearly through the program address space. The 16-bit wide Data EEPROM block resides in the upper end of the user program memory space, and is accessible using table instructions or a feature called Program Space Visibility. The Data EEPROM can be used for storing application constants and other parametric data such as lookup tables and sensor calibration constants. Finally, the Program Memory map includes configuration memory space, which can only be accessed using the table instructions. The Device Configuration Registers, which are used to configure basic parameters of device operation such as system clock source, are located in this address space. The sample program memory map shown above is for the dsPIC30F6014 device and will, of course, vary from one device to another. Note that unlike PIC MCU architectures, paging of program memory is not required with the dsPIC30F. Page 5

Data Memory Organization

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Linear Data Memory

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64 KB of addressable data space Data memory is word and byte-addressable 16-bit native data word Lower (Even) address stores LS byte Higher (Odd) address stores MS byte
0x1001 F2 0x1000 34

Data is arranged in the little-endian format

l l

2004 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC30F Architecture (Part 2)

The 64K byte of addressable linear data space contains all Special Function Registers and Data RAM. However, unlike the PIC18F family which featured a banked data memory using a register to select the required bank, the dsPIC30F family has a linear data memory space. It is both word and byte addressable by most instructions, although the native data width is 16-bits. The data is organized in Little -Endian format. That is, the Least Significant byte of a word is always held at the lower address within the word. For example, a data value hex F234 stored at location hex 1000 in data space will contain hex 34 at byte address hex 1000 and hex F2 at byte address hex 1001.

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Data Memory Map - Example*

16-bits MS Byte Address 2 KB SFR Space
0x0001

LS Byte Address
0x0000

SFR Space
0x07FF 0x0801 0x07FE 0x0800

8 KB Near Data Memory Addressable directly

8 KB SRAM Space
0x1FFF 0x27FF

X Data Space implemented as SRAM

0x1FFE 0x27FE

0x8001

0x8000

Optionally used by mapping address range into Program Space via PSV mechanism
0xFFFF

Unimplemented X Data Space * Sample Data Memory Map shown here for dsPIC30F6014 device
0xFFFE

2004 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC30F Architecture (Part 2)

A sample dsPIC30F6014 device Data Memory map is shown here. The physical end address of RAM is hex27FF for this device. The memory is depicted here with each word containing 16 bits. As mentioned earlier, each byte in the dsPIC30F data space has a unique address. Hence, two addresses are shown for each word - the even address for the least significant byte and the odd address for the most significant byte. All Special Function Registers, or SFRs, are located between the addresses hex0000 and hex07FF. The 8 Kilo Bytes of General-Purpose SRAM starts at address hex0800. This RAM is viewed as one linear X-space by MCU instructions as well as non-MAC DSP instructions. Addresses that lie in the first 8 Kilo Bytes of addressable data space may be directly addressed by an instruction. This range of memory addresses is known as the Near Data Space. The Near Data Space includes the entire range of Special Function Register addresses and ends at address hex1FFF. Addresses beyond hex8000 can be mapped into Program Space using a mechanism known as Program Space Visibility (PSV). Unlike PIC MCU devices, the dsPIC30F does not require any banking of data memory.

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DSC-MAC Instructions View of Data Memory Map - Example*

16-bits MS Byte Address 2 KB SFR Space
0x0001

LS Byte Address
0x0000

SFR Space
0x07FF 0x0801

X Data Space ( SRAM )

0x07FE 0x0800

8 KB SRAM Space

0x17FF 0x1801

0x17FE 0x1800

Y Data Space ( SRAM )

0x27FF 0x27FE

0x8001

0x8000

Optionally used by mapping address range into Program Space via PSV mechanism
0xFFFF

Unimplemented X Data Space * Sample Data Memory Map shown here for dsPIC30F6014 device
0xFFFE

2004 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC30F Architecture (Part 2)

There are some key differences between the addressing modes supported by MAC-class instructions and those supported by all other instructions. The MAC class of DSP instructions have the characteristic that they operate on 2 source operands and can simultaneously prefetch 2 words of data from RAM. A sample dsPIC30F6014 Data Memory map is shown here as seen by MAC-class instructions. The RAM is viewed as split X and Y data spaces for MAC-class DSP instructions. In most devices, X and Y RAM are equal in size. This partitioned view of the data space enables the MAC class of instructions to perform simultaneous dual data fetch operations from memory, using two independent data buses for X and Y RAM. This partitioning of X and Y RAM is not user-configurable, but varies from one device to another.

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Instruction Set Overview

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84 instructions (including DSC)

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Nearly all are one word (24 bits) Four are two words Program Flow Changes TABLE instructions Double Move Instructions DO instruction Divide instruction A = B op C Boosts code efficiency (assembly or C) (2 (2 (2 (2 cycles) cycles) cycles) cycles)

Most instructions execute in 1 Cycle, except:

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(18 cycles)

Three operand instructions

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2004 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC30F Architecture (Part 2)

Let us now discuss the instruction set supported by the dsPIC30F architecture. The dsPIC30F CPU consists of 84 different instructions. If one considers the various addressing modes possible, there are nearly 250 possible opcodes. Most of the instructions can be programmed in one instruction word. However 4 instructions require an additional instruction word; these are instructions such as Goto that involve specifying a 24bit program memory address. Most instructions execute in one instruction cycle. The exceptions are program flow changes, table instructions, double-word data moves, and DO instructions which execute in two cycles. The divide instruction is actually a single -cycle iterative instruction that needs to be repeated 18 times; the divide loop can be interrupted, however. As noted earlier, the 24-bit instruction word enables three operand instructions. This allows two source operands to be operated on, with the result stored in a third location. This maximizes code efficiency in both assembly and C language.

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Instruction Groups
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MOVE instructions MATH instructions LOGIC instructions ROTATE / SHIFT instructions BIT Manipulation instructions COMPARE / SKIP instructions PROGRAM FLOW instructions SHADOW / STACK instructions CONTROL instructions DSC instructions

2004 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC30F Architecture (Part 2)

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The instruction set may be divided into different classes: In general, Move instructions transfer data between Data RAM, special function registers or SFRs, and the W registers. Constants stored in Program Flash Memory or Data EEPROM can also be accessed using special Table instructions. Note that all instructions manipulating data can operate on either byte or word data. Math instructions include addition, subtraction, multiplication, and division. Both integer and fractional multiplication and division are supported. Logic instructions include all common Boolean operations such as And, inclusive and exclusive Or, set, clear, complement, and negate. Rotate and Shift instructions include both left and right arithmetic and logical data shifts, as well as left and right rotation of data with and without carry. The barrel shifter can shift data up to 16 bits left or right in a single instruction cycle. A rich set of Bit Manipulation instructions enable efficient execution of control operations. Individual data bits can be set, cleared, toggled, tested, and copied. In addition, Find First One from Left or Right instructions facilitate quick data searches by scanning a data word for the first non-zero bit. Another instruction, Find First Bit Change from Left, scans a word for the first bit that differs from the sign bit. Stack operations include Push and Pop instructions. C compilers can effectively use the W14 register as a Frame Pointer in conjunction with the Link and Unlink instructions, to pass parameters during subroutine calls. Program Flow instructions include Branches, Goto, Calls, and Returns. Special registers allow Do and Repeat loops to operate with zero overhead. Conditional execution is supported by Bit Test and Skip instructions and Compare and Skip instructions. Control instructions support special operations such as clearing the Watch Dog Timer, disabling interrupts for a certain period, entering the low power operation modes, or resetting the device. Finally, the DSP instructions provide support for a wide range of signal processing oriented operations such as signed and unsigned multiply and MAC, square, and Euclidean distance.

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Addressing Modes
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Generic Addressing Modes:

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Inherent Literal (Immediate) Register Memory Direct

NOP, RESET, PUSH, POP, etc. up to 16 bits of data W register array (16 x 16-bit) first 4K words (8K bytes)

Register Indirect access entire 64K data space l with Pre-inc or Pre-dec l with Post-inc or Post-dec l with signed literal offset Register Indexed base register & index register Modulo (for circular buffers) Bit-Reversed (for FFT)
Introduction to the dsPIC30F Architecture (Part 2) 11

Special Addressing Modes:

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2004 Microchip Technology Incorporated. All Rights Reserved.

The dsPIC30F addressing modes provide a high level of flexibility and orthogonality to make application code easy to develop and efficient to execute. Besides the basic addressing modes of inherent, immediate, register, memory direct, and register indirect, the dsPIC30F also provides various optional enhancements to indirect addressing, such as automatic pre or post increments or decrements, signed offsets, and indexing. Efficient execution of DSP algorithms is supported with several special addressing modes. A modulo addressing mode supports circular buffers, which are used in both MCU and DSP operations. A bitreversed addressing mode enables fast reordering of data for Fast Fourier Transform, or FFT operations.

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DSP Features

2004 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC30F Architecture (Part 2)

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Now that we have studied some fundamental facts about the dsPIC30F architecture, let us explore the Digital Signal Processing functionality of the dsPIC30F. These include several features that are fairly typical of Digital Signal Processors, but are virtually non-existent in the Microcontroller arena.

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DSP Features
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All DSP operations execute in a single cycle Single-cycle Multiply-Accumulate (MAC) instruction:
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Dual Address Generator Units (AGU) support parallel operand (data and coefficient) fetches Accumulator write-back

17 x 17-bit Fractional/Integer Multiplier

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Supports mixed-sign operations

Two 40 bit Accumulators

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Useful for complex arithmetic and multiple filters Overflow detection for accumulator values Multiple accumulator data saturation modes
Introduction to the dsPIC30F Architecture (Part 2) 13

2004 Microchip Technology Incorporated. All Rights Reserved.

Being a Digital Signal Controller, the dsPIC30F provides substantial DSP functionality to facilitate the efficient implementation of signal processing algorithms such as signal filtering or frequency spectrum analysis, or other such mathematically intensive tasks. Speed of execution is especially crucial for real-time applications, for example, processing of audio signals, because typically one needs to complete a set of computations on the current data before the next data set is sampled. This necessitates the presence of specialized on-chip hardware functionality that speeds up mathematical operations such as multiplication or division of fractional data. The dsPIC30F architecture provides a cost-effective solution for these DSP-oriented requirements. Most instructions execute in a single cycle on the dsPIC30F. This is also true for fundamental DSP operations like Multiply-Accumulate, or MAC. Moreover, the dual Address Generation Units, or AGUs, on the dsPIC30F ensure that both source operands of a multiplication operation can be prefetched simulta neously, thereby speeding up repetitive MAC operations. Two 40-bit accumulators are provided to store the temporary results of such calculations, for example, in a digital filter. One of the main benefits of having 2 accumulators is the ability to perform complex-valued computations, with 1 accumulator being used for the real part of a calculation and the other one for the imaginary part. At the same time, the value of the other accumulator can be stored back in a W register or RAM location using a feature called Accumulator Write-Back. The dsPIC30F supports a rich set of single cycle DSP instructions The dsPIC30F also supports automatic overflow detection and saturation of data, which is very useful in preventing or correcting data overflows that may result from repetitive accumulation of multiplication results. There is also a 17x17-bit multiplier that can be used for multiplying both fractional and integer values, and which also allows mixedsign multiplication. Page 13

DSP Features
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40 stage barrel shifter (up to 16 bits left or right)

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Shift accumulators, W registers or memory

Accumulator rounding during store operation

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Conventional rounding Convergent (unbiased) rounding

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Modulo addressing (for filters): both AGUs Bit reversed addressing (for FFT): one AGU Zero Overhead Instruction Loop Support
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REPEAT: Repeat next instruction N times DO: Repeat loop N times Constant or variable loop count
Introduction to the dsPIC30F Architecture (Part 2) 14

2004 Microchip Technology Incorporated. All Rights Reserved.

But thats not all! The dsPIC30F provides more features to ensure efficient DSP algorithm performance. It contains a 40-bit barrel shifter, which can shift data in the accumulator, W register or RAM up to 16-bits left or right, in a single instruction cycle. This is of immense utility, for example, while normalizing arrays of signal samples, or for unpacking data from bitstreams received over a communication channel. The data in an accumulator may be rounded before being stored. The dsPIC30F CPU supports 2 different ways of rounding, known as Conventional Rounding and Convergent Rounding. To support digital filtering, hardware support for circular buffers is provided through a special addressing mechanism known as Modulo Addressing. This feature eliminates the software overhead involved in boundary checking in circular buffers, such as those used in digital filtering algorithms for accessing data samples from delay lines. For efficient implementation of Fast Fourier Transform or FFT operations, a Bit Reversed Addressing mode is provided to speed up the re-ordering of data. Finally, in-built hardware support is provided to support zero overhead program loop control. This is accomplished through special DO and REPEAT instructions that eliminate the software overhead associated with loop management. For example, an entire array of data can be copied into another array using only two instruction words! Page 14

dsPIC30F CPU Block Diagram

Data Memory (RAM)
32K x 16 bit DSP: dual access MCU: single access Instruction Pre-fetch & Decode

Engine
Program Memory Data Access Control

DSP

Y AGU

W Array
16 x 16

X AGU

Program Memory 4M x 24 bit

MCU ALU
Address Path MCU/DSP Data Path

23-bit PC Control
DSP Data Path Program Data/Control Path

Linear

2004 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC30F Architecture (Part 2)

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This high level block diagram depicts the core elements of the dsPIC30F architecture. Notice the distinct Program Memory and Data Memory blocks, consistent with a Harvard Architecture. However, by using the Table instructions or PSV, constant data coefficients may be stored and accessed from Program Memory. This is very useful for executing digital filters in RAM-intensive applications. Another important element to observe in this diagram in the presence of two Address Generation Units, or AGUs. As mentioned in the conte xt of MAC operations, this allows accessing two data operands during a single instruction cycle, for instance: a coefficient and a data sample in a filtering operation.

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Key Support Documents

Device Selection Reference
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Document # DS70083 DS70082 DS70043 Document # DS70046 DS70030 DS51284 DS51317 DS51456

General Purpose and Sensor Family Data Sheet Motor Control and Power Conv. Data Sheet dsPIC30F Family Overview Base Design Reference

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dsPIC30F Family Reference Manual dsPIC30F Programmers Reference Manual MPLAB dsPIC C30 C Compiler Users Guide MPLAB ASM30, LINK30 & Utilities Users Guide Language Tools Libraries Users Guide

2004 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC30F Architecture (Part 2)

16

For more information, here are references to some important documents that contain a wealth of information about the dsPIC30F family of devices. The Family Reference Manual contains detailed information about the architecture and peripherals, whereas the Programmers Reference Manual contains a thorough description of the instruction set.

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Key Support Documents

Device Specific Reference

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Document # DS70118 DS70139 DS70138 DS70135 DS70116 DS70119 DS70117

dsPIC30F2010 Data Sheet dsPIC30F2011/2012/3012/3013 Data Sheet dsPIC30F3014/4013 Data Sheet dsPIC30F4011/4012 Data Sheet dsPIC30F5011/5013 Data Sheet dsPIC30F6010 Data Sheet dsPIC30F6011/12/13/14 Data Sheet Microchip Web Site: www.microchip.com

2004 Microchip Technology Incorporated. All Rights Reserved.

Introduction to the dsPIC30F Architecture (Part 2)

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For device-specific information such as pinout diagrams, packaging and electrical characteristics, the device datasheets listed here are the best source of information. All these documents can be obtained from the Microchip web site shown, by clicking on the dsPIC Digital Signal Controllers or Technical Documentation link.

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