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Scan Gates
Place
Clock Tree
Route
Functional Simulation
Module Testbench
IP
Synthesis Equivalence Checking Netlist Enhancements (Scan, Place, Route, Clock) Static Timing Analysis
Functional Simulation Sign Off
Gate-Level Domain
Comparison Of Analysis
Dynamic timing Requires exhaust set of vectors Mixing both functional and timing problems Requires more resources like run time, cpu memory, etc. Static timing Doesn't requires any set of vectors Doesn't have any problem of mixing violations Requires less resources Than DTA
Can work with any type of Logic Can work best with Synchronous logic. either synchronous or asynchronous Easy to learn Difficult to learn
5.
6. 7.
Note: This analysis is done to provide the engineer feedback in order to help modify the design and/or modify the constraints to improve the timing quality of the design.
Wireload models
RTL Coding
RTL Simulation/Verification
Synthesis
Cell Libraries
DFT insertion
FAB
Chip Testing
Net Resistance
1 0.012
2
3 4
0.030 0.045
0.060
2
3 4
0.016
0.020 0.024
CLK
Design is broken down into sets of timing paths Delay of each path is calculated Path delays are checked to see if timing constraints have been met
D Q FF2
QB --
Each path has a startpoint and an endpoint Starpoints: Input ports (A,Q) Clock pins of sequential devices (CLk) Endpoints: Output ports (D,Z) Data input pins of sequential devices (D)
1. 2. 3. 4. 5.
Clock to setup Clock to pad Paths ending at clock pin of flip flops Pad to pad Pad to set up
Clock to setup : A clock to setup path starts at flip flop clock inputs, propagates through the flip flop Q out put and any number of levels of combinational logic , and ends at non clock flip flop register inputs .
A D B D ff1 clk Q ff2 Q
Contd..
Clock to pad : It starts at a clock input of a flip-flop, propagates through the flip-flop Q output and any number of levels of combinational logic , and ends at an output pad.
A D
Q
Logic and interconne cts
pad
clock
Paths ending at clock pin of flip flops : A clock input path starts at an input of the chip. It propagates through any number of levels of combinational logic and ends at any clock pin on a flip-flop or latch enable D Q
A Inter connect logic source
Contd..
Pad to Pad up : A pad to pad path starts at an input of the chip, propagates through one or more levels of combinational logic, and end at an output pad of the chip.
pad Logic interconnect logic pad
Pad to Set up : A pad to setup path starts at an input pad of chip and ends at flip flop input.
Set up
pad
D D
Q Q
clock
Timing Violations
Setup or Hold violation: Leads to improper operation of the flip flop and the connected components. The output of the flip flop goes into a state of metastability in the case of Setup/Hold violations. Recovery and Removal Violations : Violations of Preset and Clear signal w.r.t. the Clock.
Setup Time
Setup time: the time required for the data to be stable before the clock edge
D1 Q1
FF1
0.4ns
Combo logic
D2 Q2 FF2
4.5ns
CLK
CLK
setup violation
Launch Edge Capture Edge
D2
4.9
setup time
CLK
0 0.3 4.7 5
Hold Time
Hold time: the time required for the data to remain stable after the clock edge
D1 Q1 FF1 CLK1
0.4ns 0.3ns
D2 Q2 FF2 CLK2
CLK1
Launch Edge Capture Edge
D2=Q1
CQ
CLK2
0.2
0.3 0.5
Intrinsic delays are the actual delays of the transistors inside the cell.
Setup and Hold are the times required for charging the capacitances present inside in cell.
Delay of an Inverter
VDD
When Vi = Logic 0 t = Rp * C The delay is decided by the resistance of Pmos and the output capacitance.
Vi Rp
Vo
GND Rp
Rn
The product RC is called the TIME CONSTANT This determines the delay of the cell
When Vo = Logic 1 t = Rn * C
Rn
The delay is decided by the resistance of Nmos and the output capacitance.
Insertion Delay
The delay between the clock root pin and clock sink pin of the flip flop.
Input Delay
Output Delay
There could be exceptions defined to the above behavior: Multicycle paths False paths
Multi-Cycle Paths
Those paths that require more than one clock period for execution are called
as multi-cycle paths.
Its essential that multi-cycle paths in the design be identified both for
False Paths
A path that can never be sensitized in the actual circuit These paths are those that are logically/functionally impossible The goal in static timing analysis is to do timing analysis on all true timing paths, these paths are excluded from timing analysis.
Combinational Loop
A
U1
Z
D Q
QB
U0
A Z B
D Q QB
Most STAs cant leave combinational loops in the design, because a race condition will occur. AT
Clock skew
Clock skew (timing skew) Clock signal in synchronous circuits arrives at different components at different times.
clock skew = clock insertion delay of FF1 - clock insertion delay of FF2
Clock skew
Reasons Wire-interconnect length Temperature variations
Slack
Slack is generally defined as the difference between the Required Times and Arrival Times at an end point.
Cont..
Calculation of RT from level n to level 1 Assumptions: output required time of 2.8 gate delay 0.5, wire delay 0.5
Calculation Of Slack
what is the slack..? Slack =RT -AT
Rectification Of Violations
Swapping pins -swap connections on cumulative pins or among equivalent nets
Cont..
Buffering - to improve the signal strength - to provide delay
Cloning
Cont..
Re-design Fanout Tree:
Cont..
Re-design Fan-in Tree:
Cont..
Decomposition:
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