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Basic Language Elements

VLSI DESIGN & TECHNOLOGY (EC-406)

The Basic Elements are


Identifiers Keywords Data objects Data Types Operators

Identifiers
Consists of sequence of one or more characters The legal characters are

(a z), (A . Z), (0 9) & ( _ )


First character must be a letter
Valid ( a1, b2, etc. ) Invalid ( 1a, 2b )

Identifier Naming Rules

Identifier Naming Rules

Uppercase & Lowercase are considered to be identical

E.g. Count & COUNT are identical

Two underscore characters cannot appear consecutively


Valid ( drive_bus) Invalid (drive__bus)

Keywords cannot be used as basic identifiers

Keywords
A set of reserved words in a language that have a special meaning E.g. (entity, is, port, architecture, of, begin, end, when, process, if, elsif, else, component, and, or, etc.)

Data Objects
A data object holds a value of a specified type A data object is created using an object declaration

E.g. signal a_bar : bit; This creates a data object called a_bar, which can hold bit values

Classes of Objects
Constant Variable Signal File

Constant

An object of constant class can hold a single value of a given type This value is assigned to the constant before the simulation starts The value of a constant object cannot change during the simulation A constant object is declared using the keyword constant For e.g.

constant RISE_TIME : time := 10 ns;

Variable
An object of variable class can hold a single value of a given type A variable object can be assigned different values during simulation A variable object can be declared using the keyword variable For e.g.

variable SUM : integer ;

Signal

An object of signal class can hold a list of values, which includes


The current value of a signal A set of possible future values

Signals are used to model wires and flipflops in a circuit A signal object can be declared using the keyword signal For e.g.

signal CLOCK : bit;

File

An object of file class contains a sequence of values A file object is used to model a file in the host environment Values can be read or written to the file using read or write procedures A file object can be declared using the keyword file For e.g.

file STIMULUS : bit_file;

Declaring Objects

An object declaration is used to explicitly declare an object, its type, and its class. For e.g.

signal CLOCK : bit;

Not all objects are created using explicit object declarations. E.g.

All ports of entities are signal objects

Data Types in VHDL


A data type in VHDL is associated with a set of values & operations For e.g.

BIT is a predefined type that


defines a set of values 0 and 1 Some of the operators defined on objects of BIT type are (and, or, nor, nand, xor, xnor and not)

The declarations for the predefined types of VHDL are contained in package named STANDARD

Classification of Data Types


Scalar Types Composite Types Access Types File Types

Scalar Types
Values belonging to these types are ordered (e.g. 1,2,3) and.. Relational operators can be used on these types ( e.g. 1 < 2) Four different scalar types are

Enumeration Integer Physical Floating point

Enumeration types

define a set of user-defined values These values consist of identifiers and character literals Every value has a position number associated with it Example predefined enumeration types BIT, BOOLEAN, STD_ULOGIC Example object declaration

Signal CLOCK : BIT;

Predefined Enumeration types

Example enumeration type declarations


type BIT is (0, 1); type BOOLEAN is (TRUE, FALSE); type STD_ULOGIC is (
U, X, 0, 1, Z, W, L, H, - ); ---------uninitialized forcing unknown forcing 0 forcing 1 high impedence weak unknown weak 0 weak 1 dont care

Integer Type

Defines a type whose set of values fall within a specified integer range INTEGER is the only predefined integer type of VHDL The minimum range of values covered by INTEGER TYPE should be (2E31 1) to +(2E31 1) Example object declaration

Signal sel : INTEGER;

Floating Point Type


Has a set of values in a given range of real numbers REAL is the only predefined floating point type of VHDL The minimum range of values covered by REAL type should be 1.0E38 to +1.0E38 Must provide at least six decimal digits of precision Example object declaration

variable length : REAL;

Physical Type

Contains values that represent measurement of some physical quantity like time, voltage etc. Values of this type are expressed as integer multiples of a base unit TIME is the only predefined physical type in VHDL The range of TIME is same as integer i.e. (2E31 1) to +(2E31 1)

Example Physical Type Declaration


type CURRENT is range 0 to 1E9 units nA; -- (base unit) uA = 1000 nA; mA = 1000 uA; Amp= 1000 mA; end units;
variable base_current : CURRENT;

Composite Type
Represents a collection of values These are of two types

Array Record

Array is a collection of values of same type Record is a collection of values that may belong to different types

Example Array Declarations


type type type type ADD_WORD is array (0 to 15) of BIT; DATA_WORD is array (0 to 7) of BIT; STACK is array (0 to 255) of DATA_WORD; ROM is array (0 to 65535, 0 TO 7) of BIT;

Creating objects of Array type signal address_bus : ADD_WORD; variable accumulator : DATA_WORD; variable flag_register : DATA_WORD; variable stack_memory : STACK; variable prog_memory : ROM;

Assigning values to Arrays


address_bus <= X7FFF; address_bus (8 to 15) <= XFF; accumulator := 01101010; flag_register(3) := 1; stack_memory(127) := flag_register; stack_memory(127) (3) := 0; prog_memory (127) := accumulator; prog_memory (127, 3) := 0;

Constrained & Unconstrained Arrays

Constrained Arrays the number of elements in the array type is specified explicitly. For e.g.
type ADD_WORD is array (0 to 15) of BIT;

Unconstrained Arrays - the number of elements in the array is not specified in the type declaration Instead, the number of elements in the array is specified during object declaration

Unconstrained Arrays

Declaring unconstrained arrays


type DATA is array (INTEGER range <>) of BIT;

Creating objects of unconstrained arrays


signal data_bus : DATA (0 to 7); signal add_bus : DATA (0 to 15);

Predefined unconstrained array types

BIT_VECTOR an array of bits variable accumulator : BIT_VECTOR(0 to 7); STRING an array of characters

Record Types
Are similar to structures in C or record data types in Pascal Example record type declaration

type PSW is record accumulator : BIT_VECTOR( 0 TO 7); flag_register : DATA_WORD; end record;

Access Types
Values belonging to an access type are pointers to dynamically allocated object of some other type They are similar to pointers in C and Pascal E.g. type top_of_stack is access STACK;

File Types
Objects of file type represent files in the host environment Provide a mechanism by which a VHDL design communicates with the host environment For e.g. type names is file of STRING;

Subtypes
A subtype is a type with a constraint For e.g.

subtype short is INTEGER range -128 to 127;

The set of operations defined on subtype are same as that of its base type

Operators

The predefined operators in VHDL are classified in 6 categories


1.

2.
3. 4.

5.
6.

Logical Relational Shift Adding Multiplying Miscellaneous

Logical operators

These are
and or not nand nor xor xnor

Relational operators

These are
= /= < <= > >= equal to not equal to less than less than equal to greater than greater than equal to

Shift operators

These are
sll srl sla sra rol ror

Adding operators

These are
+ (addition) - (subtraction) & (concatenation)

Multiplying operators

These are
* (multiplication) / (division) mod (modulus) rem (remainder)

Miscellaneous operators

These are
abs (absolute) ** (exponentiation)