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Misconception
Only if the system processes two different instructions simultaneously can it be considered parallel
A system that performs different operations on the same instruction is not considered parallel.
example of parallelism in a uniprocessor system. Each stage of a reconfigurable arithmetic pipeline has a multiplexer at its input. The multiplexer may pass input data, or the data output from other stages, to the stage inputs. The control unit of the CPU sets the select signals of the multiplexer to control the flow of data, thus configuring the pipeline.
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A Reconfigurable Pipeline With Data Flow for the Computation A[i] B[i] * C[i] + D[i]
Data Inputs
0 * LATCH 1 MUX 2 3 S1 S0
0 0
0 | LATCH 1 MUX 2 3 S1 S0
x x
0 + LATCH 1 MUX 2 3 S1 S0
0 1
0 1 MUX 2 3 S1 S0
1 1
To
memory
and registers
Although arithmetic pipelines can perform many iterations of the same operation in parallel, they cannot perform different operations simultaneously. To perform different arithmetic operations in parallel, a CPU must include a vectored arithmetic unit.
A vector arithmetic unit contains multiple functional units that perform addition, subtraction, and other functions. The control unit routes input values to the different functional units to allow the CPU to execute multiple instructions simultaneously.
+ *
Data Inputs
%
AB+C DE-F
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parallelism by having more than one processor performing tasks simultaneously. Since multiprocessor systems are more complicated than uniprocessor systems, there are many different ways to organize the processors and memory
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Flynns Classification
SISD: Single instruction with single data SIMD: Single instruction with multiple data MISD: Multiple instruction with single data MIMD: Multiple instruction with multiple
data
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Topologies
Topology of a multiprocessor system refers to the pattern of connections between its processors. Various factors, typically involving a cost-performance tradeoff, determine which topology a computer designer will select for a multiprocessor system.
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Types of Topology
Shared Bus Topology Ring Topology Tree Topology Mesh Topology Hypercube Topology Completely connected Topology
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exclusively through this bus. However, the bus can only handle only one data transmission at a time. In most shared busses, processors directly communicate with their own local memory.
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Ring Topology
between processors instead of a shared bus. This allows all communication links to be active simultaneously. Data may have to travel through several processors to reach its destination
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Tree Topology
between processors; each having three connections. There is only one unique path between any pair of processors
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Mesh Topology
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Hypercube Topology
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the processors are completely connected. Every processor has (n-1) connections, one to each of the other processors. This increases the complexity of the processors as the system grows, but offers maximum communication capabilities.
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