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# DELAYS IN ASIC DESIGN

TYPES OF DELAYS

Gate delay Intrinsic delay Net delay Transition or Slew delay Propagation delay Contamination delay

## DEPENDENCE OF DELAYS ON VARIOUS FACTORS

Input capacitance of the logic gate is a function of output state, output loads and input slew rate. Internal timing arcs and output slew rate is a function of switching input(s). Capacitance of the wire is dependent on frequency. Internal timing arcs are a function of input slew rates. Output slew rate is a function of input slew rate on each input. Wires exhibit RLC characteristics instead of lumped RC.

## GATE DELAY / CELL DELAY

Gate delay = function of (input transition(slew) time,Cnet+Cpin) where Cload=Cnet+Cpin Cnet-->Net capacitance Cpin-->pin capacitance of the driven cell

INTRINSIC DELAY

Intrinsic delay is the delay internal to the gate. It is caused by the internal capacitance associated with its transistor. This delay is largely dependent on the size of the transistors forming the gate.

## NET DELAY OR WIRE DELAY

Net delay is the difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net.

## WIRE / EXTRINSIC DELAY

There are several factors which affect net parasitic: Net Length Net cross-sectional area Resistively of material used for metal layers (Aluminum vs. copper) Number of vias traversed by the net Proximity to other nets (crosstalk)

## NET / INTERCONNECT DELAY

Interconnect introduces capacitive, resistive and inductive parasites. All three have multiple effects on the circuit behavior. increase in propagation delay increase energy dissipation introduce extra noise sources

Capacitance

## Capacitance can be modeled by the parallel plate capacitor model. C = ( / t).WL

Resistance R= (.L)/ (H.W) = (. L)/ Area L --> length W --> width --> resistivity (ohm-m)

## VARIOUS MODELS FOR WIRE DELAYS

TRANSITION DELAY

Transition or slew is the time it takes for the pin to change state

## RISE TIME FALL TIME

PROPAGATION DELAY
Propagation delay is the time required for a signal to propagate through a gate or net.

Propagation delay of a gate or cell is the time it takes for a signal at the input pin to affect the output signal at output pin. For any gate propagation delay is measured between 50% of input transition to the corresponding 50% of output transition

PROPAGATION DELAY
There are 4 possibilities:

Propagation delay between 50 % rising to 50 % of output rising. Propagation delay between 50 % rising to 50 % of output falling. Propagation delay between 50 % falling to 50 % of output rising. Propagation delay between 50 % falling to 50 % of output falling.

## of Input of Input of Input of Input

PROPAGATION DELAY

For net propagation delay is the delay between the time a signal is first applied to the net and the time it reaches other devices connected to that net. Propagation delay is taken as the average of rise time and fall time i.e. Tpd= (Tphl+Tplh)/2. Propagation delay depends on the input transition time (slew rate) and the output load.

CONTAMINATION DELAY

Best case delay from valid input to valid output. i.e. minimum propagation delay.

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