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Chap. 8 Datapath Units: Multiplier Design

Prof. An-Yeu Wu Undergraduate VLSI Design Course
Updated: June 12, 2002

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Several Implementations of Multipliers

Array Multiplier 2s Complement Array Multiplier Serial Multiplier CSD Code String-encoding Multiplier Modified Booth-encoded Multiplier Implementation (Chap. 8.2.7.2)

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6-by-6 Multiplication

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Wallace-Tree Multiplication
FA is a ones counter: Take A, B, and C inputs and encodes them on SUM and CARRY outputs.
A 1-bit full adder (FA) provides a 3:2 compression in the number of bits. A+B+C=2C+S
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7-bit Wallace tree addition

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Ex: 66 Wallace Multiplier

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Example
In a 32-bit multiplier, the maximum number of partial products is 32 and the compressions are 32 22 16 12 8 6 4 3 2 => There are 9 Full-adder (FA) delays in the array

1. c.f. Array multiplier (Booth-recoded) =16 partial products to be summed up. 2. Can be used together with Booth-encoding scheme
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Wallace Tree Multiplier

MxN Booth-encoded multiplier (IEEE JSSC, vol.1,no.2, June 1993)

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A typical delay distribution of the output of Wallace tree section

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Extension

32-bits Wallace-tree multiplier has 9 FA delays in the array Questions:

1. For a 64-bit multiplier, what is the minimum adder delay? 2. Is there any way to reduce the delay by other compression scheme?

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Approach:
Using 4:2 compression adder
The 4:2 compression (really 5:3) has three XOR delays in the SUM path. c.f.: Four XOR delays will be present if two adders are used

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Referenced Paper
A 54x54 regularly structured tree multiplier: IEEE Journal of Solid-State Circuits (vol. 27, no.9, 1992)

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Chap. 8.2.7.2: Implementation of Booth-encoded Multiplier

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Implementation: Radix-n Multiplication

Modified Booth-recoding Values Xi-1 Xi 0 0 0 0 1 1 0 0 1 1 0 0 Xi+1 0 1 0 1 0 1 OPERATION add0 add2 sub1 add1 sub1 add1 NEG 1 0 1 0 1 0 ZERO TWO 1 0 0 0 0 0 0 1 0 0 0 0

1
1

1
1

0
1

sub2
add0

1
0

0
1

1
0

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16*16 Booth Multiplier

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Array schematic

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Array Floorplaning

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First Rank Schematic

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Booth decoding Schematic

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Booth-Add-16 rank floorplan

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Adder rank schematic

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Booth gate

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Array adder layout

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Carry Propagate Adder

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Homework #6 (Cancelled)
Design an 8-bit Modified Booth-encoded (or String-encoding based) Wallace-tree Multiplier
1. 2. 3. 4. 5. 6.
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Draw the schematic diagram of your design. Verify your design first using C/C++ or Matlab programs. Write down the Verilog/VHDL code and perform simulation. Verify your Verilog/VHDL codes. That is,check your simulation results with the C/C++/Matlab results. Show your (1) Schematic (2) Source code (3) Simulation results in your report. Due date: June 28, 2002.
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