MSP430G2553 CPU

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MSP430G2553 CPU Agenda

CPU Feature Registers Addressing Modes Instructions

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MSP430G2553 CPU Features

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CPU Features
Designed for modern programming techniques
Calculated branching, Table processing

RISC Architecture
27 Instruction and 7 addressing modes

Orthogonal architecture
Every instruction usable with every addressing mode

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CPU Features
Access entire memory range
No paging required

Single-cycle register operations

Predicted execution time

Full register access

Including program counter, status registers, and stack pointer

Direct memory-to-memory transfers without intermediate register holding

Better register utilization

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MSP430G2553 Registers

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CPU Block Diagram:

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Dedicated RO R1 R2 R3
PC SP

General Purpose R4 R5

SR
CG

. .

R15
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Program Counter (PC)

PC R0
Holds address of next instruction to execute Holds even number
Since all instructions size are even number (2, 4, 6 bytes)

16bits wide Can address 64KB space

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Stack Pointer (SP)

SP R1 CPU to store the return addresses
Subroutine/interrupt call

Predecrement, postincrement scheme

PUSH Decrement SP then WRITE POP READ and then Increment SP

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Status Register (SR) R2

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Constant Generator (CG)

R3
Stores the constant values used in immediate addressing mode Assembler automatically uses it Source-only register Applications cannot use this register as destination Only assembler could use

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General-Purpose Registers
R4 to R15 Can be used for Data registers Address pointers or Index values
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MSP430G2553 Addressing Modes

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Addressing Modes

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Register Addressing Mode

Example: MOV R10,R11

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Indexed Addressing Modes

Example: MOV 2 (R5) , 6 (R6)

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Symbolic Mode:
Example: MOV EDE,TONI; EDE = (PC + X) TONI = (PC + Y)

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Absolute Mode:
Example: MOV &EDE,&TONI ; EDE = 0F016h ; TONI = 01114h

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Indirect Register Mode:

Example: MOV.B @R10,0(R11)

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Indirect Auto-Increment Mode:

Example: MOV @R10+,0(R11) ; R10 auto incremented

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Immediate Mode:
Example: MOV #45h,TONI

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MSP430G2553 Instructions

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Instruction Set:
27core instructions and 24 emulated instructions. Core ins->unique op-codes Emulated-> code easier to write and read

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Double-Operand:
Word or Byte instruction (.B,.W) Examples: MOV (.B) ADD (.B) SUB (.B) MUL (.W) ADDC (.B)

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Single-Operand:
Example: RRC (B) RRA (B) SWP (B) PUSH (.B)

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Jump:
Example: JMP JC JNC JN

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Q&A

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