VLSI For Electrical Engineering

Dr. Veena S Chakravarthi scveena@gmail.com Professor Department of Electronics & Communication Engineering BNMIT

Agenda
Introduction- History, Revolution, growth Understand the core device - MOS Shrinking MOS / Scaling Design Methodology SOC Product development flow Getting ready for semiconductor Industry Summary

Guess and Identify..

ook closely n' guess what they cud be...

So it is

Smart home control application

History
Silicon R evolution in 40 years !!
19 8 19 5 58 1997 1997

F s ine r t dc c it( em n m, 1 5 ir t t gae ir u g r a iu ) 9 8 Ja kS c . K y , T x s I s r m ns ilb e a n tu e t C na e f ec m o e t , t r et p s o t in d iv o p n ns h e y e : t a s t r r s t r a dc p c o s r n is o s e is o s n a a it r

In P tiu II, 1997 tel en m C ck: 233M z lo H N m er o tran u b f sisto 7.5 M rs: G L g : 0.35 ate en th

Gorden Moore

Moores Law Feature Size

Growth
1997 devices (0.25 m)
1 cm 1 mm 0.1 mm 10m 1 m 0.1 m 10 nm 1 nm 1

Chip size (1 cm)

Diameter of Human Hair (70 m)

1996 devices (0.35 m)

2007 devices (0.1 m)

Silicon atom radius (1.17 ) X-ray Wavelength (0.6 nm)

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1 Micron, 1 m = 1000 nM 1 nM = 10 A0 (Angstrom)

Deep UV Wavelength (0.248 m)

Moores Law Some analogies

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Transistor- structure

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Transistor- Function

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Transistor- Characteristics

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Transistor- Connections

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Transistor- application
Vss
S
n+ p-

Vdd
n+

D
S

Vgs

>= Vth ON < Vth OFF

N-Transistor

Substrate

Vgs

- Substrate , Diffusion , Gate-Oxide(SiO2) & PolySi gate - Source , Drain , Gate & Substrate
Vss
D
p+ n-

G
p+

Vdd
S
D

G
Vgs <= Vth > Vth ON OFF

P-Transistor

Substrate

Vgs

- MOS Transistor is Bi-Directional Device

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Transistor- application
N-Switch
Vdd G
Vgs

Complimentary Switch
(Transmission Gate) s b S=0 a -s b

D S Vss

a S=1

Transistor Schematic s

P-Switch
Vdd
Vgs

a b S=1 -s Logic Symbol

S G D Vss

a S=0

S=1 : Output b is Good 0 / Good 1 Depending on input a. S=0 : Switch is OFF No path from a to b.
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CMOS logic
Vdd a x Vss a
0 1

Vdd a a b Vss a b
0 0 1 1 0 1 0 1

Vdd b x a x
1 1 1 0

a b b a
0 0 1 1

x b
0 1 0 1

Vss

x
1 0

x
1 0 0 0

Circuit Symbol

a x b Circuit Symbol

a x b Circuit Symbol

INVERTER

NAND2

NOR2
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Inverter Mask Set

Transistors and wires are defined by masks Cross-section taken along dashed line

GND nMOS transistor substrate tap pMOS transistor well tap

VDD

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Inverter Layout

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Scaling

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Scaling- FET

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Short Channel Effect

2 D Field effects
Drain Induced Barrier Lowering DIBL Mobility reduction Threshold reduction

High Electrical field in the channel

Carrier velocity saturation Impact Ionization Hot Electron effect Gate oxide charging Parasitic Bipolar effect

Decrease of Source Drain distance

Punch through Channel length modulation
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Wire Scaling
45 40 35 30

Delay (ps)

25 20 15 10 5 0 0.65um 0.5um 0.35um 0.25um 0.18um 0.13um 0.1um

Gate Cu Interconnect Al Interconnect Cu + Gate Al + Gate

Mark Bohr, Intel, IEDM 95 Wire 43um long 0.8um high Scaled width
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VLSI Design

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25

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Design Description Domains

Behavioral Domain
Application OS Subroutines Instruction

Structural Domain
Chip / System RISC Processor Gates. Adders, Registers Transistor Circuit Abstraction Layer Transistor Cells Modules Chips , Boards & Boxes RTL, Logic Abstraction Layer

Architectural Abstraction Layer

Physical Domain
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RTL Model Sequential Machine & Finite State Machine (FSM)

Generalized Mealy Model for Synchronous Sequential Machines

IN [ 1 : N ] CS [1 : K]
Combinational Logic ( C / L )

OUT [ 1 : M ] NS [ 1 : K]

D Reg

OUT = NS =

F1 (IN , CS); F2 (IN , CS)

Clock

Iterative Model for Synchronous Sequential Machines

Stage 1 D Stage 2 Stage 3

D q Reg
Clk (1)

SYS_CLK

C/L 1

D q Reg
Clk (2)

C/L 2

D q Reg
Clk (3)

C/L 3

Stage 4 D D q

Reg

Clk (4)

SYS_CLK

t1

T
T

Timing Constraint

t2 >= t clk-q +

t3 ( ) max t C/L + t setup

t4
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System Design Parameters to Consider

Performance Size of Die Time to Design Ease of Test Generation

Speed , Power , Function & flexibility. ( hence cost of Die). ( hence cost of Engineering & Schedule ). ( hence cost of Engineering & Schedule ).

Implementation Options :
Gate Array Performance Die Size Design Effort Test Generation Effort Low Large Low Low Cell Based Medium Small Medium Medium Full Custom High Smallest Very High High

NOTE : Test Generation has two aspects. 1. Design or Function Test . & 2. Manufacturing Test.
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Structured Design Strategies

Hierarchy : Successive refinement of design abstraction to Manage complexity. Structural hierarchy within one Abstraction Level. Regularity: Reuse blocks designed once , many times to improve design productivity. Modularity : Module -> Sub-Module - > .-> Leaf Cell. Well defined functionality & Interface. Locality : Well characterized module interface to hide internal design details.
- These have a strong Parallel to Object oriented Software design Methodology.

Hierarchy Regularity Modularity Locality

: Successive refinement of SW Design into lower & lower functions/objects. : Repetitive use of Objects. Object Reuse ( Object Factory.). : Well defined object functionality & interface to enable reuse of the Objects. : Local variables & Methods hidden from outside world.
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Structured Software & VLSI Hardware Design

Software Hierarchy Regularity

Subroutines , Libraries Iteration, Code-sharing, OO-Procedures

Hardware
Modules Data path Module Reuse, Regular arrays,

Modularity Locality

Well Defined Well defined Subroutine Module Interface, Interface Timing & Loading Data. Local Scoping, No Global Variables. Local Connection Thro Floor-planning. Registered I/O.

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SOC
What is SoC? System-on-Chip An IC that integrates the major functional elements of a complete end-product into a single chip.

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SOC (Contd.)
An SOC contains
Reusable IP Embedded processor/Memory Real world interface Mixed signal blocks Programmable hardware

Has more than 500K gates Use 0.25um technology or below Not an ASIC

SOC design methodology revolution

Product Life cycle development

Idea Stage Idea can be from

anywhere Idea should be in sync with the companys objective Core Resources available at Companys reach.

Business case Marketing Responsibility

Market analysis Costing and ROI worked out Competitive analysis and differentiators identified

Product Feasibility System Engineering

Responsibility Application scenarios Feature definition Feasibility with Engineering Product specification, HW/SF/DSP needs identified

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Product Life cycle development (Contd.)

Product commit Management commits to invest Engineering commits to develop

Tape Out decision Marketing Responsibility Market analysis Costing and ROI worked out Competitive analysis and differentiators identified

Chip Validation and Engineering Samples System Engineering Responsibility Application scenarios Feature definition Feasibility with Engineering Product specification, HW/SF/DSP needs identified

Product Release System Engineering Responsibility Application scenarios Feature definition Feasibility with Engineerin Product specification, HW/SF/DSP needs identified

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A Typical Design Flow - Simplified

Back End Design Front End Design Design Concept A HDL Capture Schematic Capture Floor Plan Tech_Dbase SC & Block P&R Tech_Dbase C

HDL Simulation

Pad Ring & Power P&R

RTL SIM - OK ? Y HDL Synthesis Tech_Dbase

Net & Parasitics Extraction Y Back Annotation

Tech_Dbase

Gate SIM - OK ? Y B

Gate SIM - OK ? Y

Mask Data Generation

To Si Foundry

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Skill Set Requirement

VLSI specific skills: Understanding of the basic CMOS process VLSI design flow and entry/exit criteria for each phase Capability to visualize the logic for a function. HDL coding to realize the logic EDA Tool flow and usage Scripting skills for data analysis C+ programming skills for co verification Logic parameters and their relevance Additional knowledge Processor architecture Interfacing Timing requirements Clocking strategy
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Opportunities
Product development Services
Design houses Board design houses System integration services Test houses Repair and maintenance services Verification services Total Solutions Quicker shuttles Characterization

Product companies

Fabrication houses Certification bodies Consultancy services

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Opportunities
Larger system development State of Art development suites Close relationship with customers and suppliers Challenges at all phases of the development Opportunity to become Multi skilled World connect Need to do distributed development taking advantage of geographic locations Global coordination

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What does this mean?

Do it ..
Right First time Communicate clearly Quick Defined matured process Compliant to process Acquire multiple skills Learn new development suites Learn different languages Analyze every issue

Some Tips for You!

Find application for your task Communicate Well Be open for Learning Get broader perspective Detailing Be a perfectionist Plan you career in advance Be patient Develop good attitude Be a good Team player

Summary
VLSI - Revisited Understand the core device - MOS Shrinking MOS / Scaling
Design Description Domains : Behavior , Structure & Physical. RTL Design , Synchronous Sequential Machine , FSM Performance , Die Size , Design Effort , Test Generation Effort.

System Design Parameters Design Strategies SOC Product development Cycle Typical Design Flow Getting ready for Semiconductor Industry
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Get yourselves equipped to be a part of exciting fast growing field

VLSI needs you, Get Ready!