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Kartik Mohanram Dept. of Electrical and Computer Engineering Rice University, Houston, TX
UCF generation
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Compile!
Select the decoder2to4 module and double-click the Synthesize XST button. Note that Xilinx displays all allowed options for the selected file in the project. For example, selecting the io.ucf file does not provide options like synthesis, etc. since it really is not a Verilog module. Synthesis will take some time. If successful, you will see a green check-mark Double-click Generate Programming File to generate the bit-file You can expand the synthesis tab and look at the synthesis report, warnings, critical path delay, etc. Errors and warnings Heed them and you will learn as you go Ask labbies
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