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ILP Speculation
BY REJIN PAUL Lecturer,CSE Dept.
Outline
Speculation to Greater ILP Speculative Tomasulo Example
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Essentially a data flow execution model: Operations execute as soon as their operands are available
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Modern processors such as PowerPC 603/604, MIPS R10000, Intel Pentium II/III/4, Alpha 21264 extend Tomasulos approach to support speculation
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FP Op Queue
Reorder Buffer
FP Regs
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Thus, the ROB supplies operands in interval between completion of instruction execution and instruction commit
ROB is a source of operands for instructions, just as reservation stations (RS) provide operands in Tomasulos algorithm ROB extends architectured registers like RS
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2. Destination
3. Value
4. Ready
Indicates that instruction has completed execution, and the value is ready
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Instructions commit values at head of ROB placed in registers Reorder As a result, easy to undo Buffer speculated instructions FP Op on mispredicted branches Queue FP Regs or on exceptions
Commit path
Res Stations FP Adder
3/24/2013 CPE 731, ILP4
Newest
Reorder Buffer
F0 LD F0,10(R2) N
ROB1
Oldest
Registers
Dest Dest Reservation Stations
FP adders
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Newest
Reorder Buffer
F10 F0 ADDD F10,F4,F0 LD F0,10(R2) N N
ROB2 ROB1
Oldest
Registers
Dest 2 ADDD R(F4),ROB1 Dest Reservation Stations
FP adders
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Newest
Reorder Buffer
F2 F10 F0
N N N
Oldest
Registers
Dest 2 ADDD R(F4),ROB1 Dest 3 DIVD ROB2,R(F6) Reservation Stations
FP adders
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Reorder Buffer
F0 F4 -F2 F10 F0
ADDD F0,F4,F6 LD F4,0(R3) BNE F2,<> DIVD F2,F10,F6 ADDD F10,F4,F0 LD F0,10(R2)
N N N N N N
Newest
Oldest
Registers
Dest 2 ADDD R(F4),ROB1 6 ADDD ROB5, R(F6) Dest 3 DIVD ROB2,R(F6)
FP adders
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Reservation Stations
FP multipliers
17
Reorder Buffer
Oldest
Registers
Dest 2 ADDD R(F4),ROB1 6 ADDD ROB5, R(F6) Dest 3 DIVD ROB2,R(F6)
FP adders
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Reservation Stations
FP multipliers
18
Reorder Buffer
Oldest
Registers
Dest 2 ADDD R(F4),ROB1 6 ADDD M[10],R(F6) Dest 3 DIVD ROB2,R(F6)
FP adders
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Reservation Stations
Reorder Buffer
Oldest
Registers
Dest 2 ADDD R(F4),ROB1 Dest 3 DIVD ROB2,R(F6) Reservation Stations
FP adders
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Reorder Buffer
Oldest
Registers
Dest 2 ADDD R(F4),M[20] Dest 3 DIVD ROB2,R(F6)
FP adders
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Reservation Stations
Newest
Reorder Buffer
Oldest
Registers
Dest 2 ADDD R(F4),M[20] Dest 3 DIVD ROB2,R(F6)
FP adders
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Reservation Stations
Newest
Reorder Buffer
Oldest
Registers
Dest Dest 3 DIVD val3,R(F6) Reservation Stations
FP adders
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Newest
Reorder Buffer
Oldest
Registers
Dest Dest Reservation Stations
FP adders
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Newest
Reorder Buffer
Oldest
Registers
Dest Dest Reservation Stations
FP adders
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Reorder Buffer
What about memory hazards???
Oldest
Registers
Dest 2 ADDD R(F4),ROB1 Dest 3 DIVD ROB2,R(F6) Reservation Stations
FP adders
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THANK YOU
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