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PWM
PWM Features
General Features
Four Channels, one 16-bit counter per channel, One common clock generator, providing 13 different clocks,
One Modulo n counter providing eleven clocks, Two independent linear dividers working on modulo n counter output,
Channel Programming
Independent enable/disable commands, Independent clock selection, Independent period and duty cycle, with double buffering system, Programmable selection of the output waveform polarity, Programmable center or left aligned output waveform.
PWM
4 Multiplexed Channel outputs with PIOA lines Dedicated high current output pad
- Multiplexed to PA0, PA1 and PA2 (respectively for PWM0, PWM1 and PWM2) allow the user to drive external circuitry with load current up to 16 mA (instead of 8 mA for standard pads)
PWM
Peripheral B
Select between Peripheral A or B, respectively, in PIO_ASR or PIO_BSR in order to select the PWM peripheral output channel(s) on the right pad(s).
PWM
PWM Architecture
2- Channel Modules:
Clock Selector Channel Running Mode Manager Duty Cycle and frequency Control Counter value Update register
PWM
PREB
DIVB
PREA
DIVA
/1 /2 /4 /8 /16
MCK
1, ,1/3,..,1/255
1, ,1/3,..,1/255
CLKA
CLKB
PWM
PWM_ENA (Enable Register) CHID3 CHID2 CHID1 CHID0 PWM_SR (Status Register)
3 0
The user can use the same control panel at interrupt level plus the dedicated mask register
PWM_IDR (Interrupt Disable Register)
3 0 3 0
PWM_IER (Interrupt Enable Register) CHID3 CHID2 CHID1 CHID0 PWM_IMR (Interrupt Mask Register)
3 0
PWM
Disable the PIO lines and select the right peripheral between A or B at multiplexing level. For power saving consideration, the PWM s clock is stoppped at Power Management Controller level by default.
Set up the targeted clocks which will be used for the 4 PWM Channels.
Channel Enabling
Interrupt Enabling
PWM
Per channel:
Channel Mode Register: Select the running mode of the channel Duty Cycle Register: 16-bit value to select the duty cycle of the signal Period Register: 16-bit value to select the period of the signal Counter Register: counter value Update Register: Specific register to modify, synchronously, the Duty Cycle Register or the Period Register.
PWM Channel 0,1,2 or 3
Period Control Update Register Duty Cycle Control
PWM Controller
PWM pad
Comparator
CLKA CLKB
MCK. down to MCK/1024
Interrupt
9
PWM
CLKA CLKB
/1 /2 /4 /8 /16 /32 /64 /128
CPRE
At Channel level, the Channel Mode Register allows the user to choose between the 13 sources from the clock generator
Channels Counter
/256
/512 /1024
Clock Generator
10
PWM
N value
CDTY
The duty cycle quantum depends on the value written in Period Register:
The M value is the required number of event in order to complete one PWM channel period (or half period in center-aligned mode) PWM_CPRD (Channel Period Register)
15 0
M value
CPRD
The PWM Channel period being equal to M source period. N will be from 0 up to M value. The higher M value, the higher the N value can be, the lower the quantum.
11
PWM
In this first choice, the duty cycle quantum will be 1/75 of a period
CLKA CLKB Clock Generator on 750 kHz (/64) = 10 kHz
48 MHz
Clock Generator
For the same period, the duty cycle quantum will be 1/4800 of a period.
CLKA CLKB
48 MHz
Clock Generator
48 MHz
10 kHz
12
PWM
Before to enable the PWM Channel at PWM Controller level (PWM_ENA Register): The user will be able to write directly into the PWM_CDTYx or PWM_CPRDx of this channel, respectively, for a duty cycle or period change. As soon as this PWM channel has been enabled: It is not possible to write into these previous registers. The user will have to use the Channel Update Register in order to modify one of the previous value.
The contain of the Update register is put into the PWM_CDTY or PWM_CPRD according to the value of CPD value in PWM_CMR
PWM_CMRx (Channel Mode Register)
10 3 0
CPD
CPRE
PWM
Note: It is not possible to modify, in the same PWM period for one channel, the duty cycle AND the period values.
14
PWM
Modifying duty cycle or period value in channel 1 can be possible without overlaying risk at PWM_CUPD level.
15
PWM
PWM_CPRD
PWM_CDTY 0
CPOL= 0
CPOL= 1
16
PWM
The left-aligned working mode does not allow to avoid overlapped transition in Multi-channel use
PWM_CPRD0 PWM_CDTY0 In Left-aligned Mode: One event depends on the duty cycle value and the other depends on the period value. For the same period, there will be overlapped event
Channel 0 Output
PWM_CPRD1
PWM_CDTY1
17
PWM
PWM_CPRD
PWM_CDTY 0
CPOL= 0
CPOL= 1
18
PWM
The center-aligned working mode allows to avoid overlapped transition in Multichannel use
PWM_CPRD0 PWM_CDTY0
Channel 0 Output
PWM_CPRD1 PWM_CDTY1
19