Microcontroller

Alexander Kler, Matthias Fgger SS 2012 course

Featuring Today: Communication

Training Objectives
3.4.4 Glitches (!) 3.6.4 TWI 3.8.4 LCD 3.8.2 Debouncing

Basics

Serial mC mC communication Example mC1, mC2 in 10m distance mC1 wants to trigger mC2 to do something Proposal 1 single line

mC1

PORTA1

PIND2 (INT0) mC2

sender

receiver

mC1: write 0/1 mC2: trigger on rising edge at INT0

Basics

Serial mC mC communication Example mC1, mC2 in 10m distance mC1 wants to trigger mC2 to do something Proposal 2 line + common ground

mC1

PORTA1 GND

PIND2 (INT0) mC2

sender

receiver

mC1: write 0/1 mC2: trigger on rising edge at INT0

Basics

Serial mC mC communication Example mC1, mC2 in 10m distance mC1 wants to trigger mC2 to do something Proposal 3 pullup + common ground
Vcc mC1 PORTA1 GND PIND2 (INT0) mC2

sender

receiver

mC1: write 0/X mC2: trigger on rising edge at INT0

Basics

Serial mC mC communication Example mC1, mC2 in 10m distance mC1 wants to trigger mC2 to do something Proposal 4 driver + common ground
(Vcc) mC1 PORTA1 GND PIND2 (INT0) mC2

sender

receiver

mC1: write 0/1 mC2: trigger on rising edge at INT0

Basics

Serial mC mC communication Example mC1, mC2 in 10m distance mC1 wants to trigger mC2 to do something Proposal 5 differential signalling

mC1

PORTA1

PIND2 (INT0) mC2

sender

receiver

mC1: write 0/1 mC2: trigger on rising edge at INT0

Differential signalling

Do not need common ground

sender

receiver

from [Texas Instruments manuals]

Can detect open cable More resistive to noise lower voltage swing possible (LVDS)

Differential signalling

Failure detection
recognize open/ short cable in case of failure: output stable 1

from [Texas Instruments]

Differential signalling

Example
LVDS Quad CMOS Differential Line Receiver
from [National Semiconductor]

[A1] [B1]

Logical Function

Logical function

Differential signalling

Example Application
Transmit signal over printed circuit board, cable (Cat-5), etc. transport medium must have controlled impedance of e.g. 100 Ohm

from [National Semiconductor]

General

A word of warning
Whenever two distinct, unsynchronized clock domains exchange data, the possibility of metastability is non-zero!

Triggering is nice, but there is more!

More complex communication transmitting complete messages recognize repetitive bits, e.g. 00111 error detection, ... communication between mC and PC communication between mC and sensor/actuator typical, widely used communication protocols

Categories

Who initiates communication master/slave vs. equal parts Bidirectional/unidirectional at a time Full-/half-duplex Transmitter provides clock or not (A)Synchronous Means to physically communicate Single ended Differential signalling Wireless bus vs. p2p & serial vs. parallel (bus addressing, mutex)

Basics

The ATmega1280 TWI Two-Wire serial Interface SPI Serial Peripheral Interface USART Universal Synchronous/Asynchronous Receiver/Transmitter

UART (SPI)

on bit level, does not specify physical layer

asynchronous, serial TX, RX per line, two lines for full duplex

TX reg fT sender

TX

RX

RX reg fR receiver

UART (SPI)

bit level specification

D0 D1 start D2 D3 D4 Dn (P) stop (stop)

1/B, baud rate B

General D{E|O|N}S, S in {1,2} Atmega16 D in {5,..,9}

Example. 7E1
D0 D1 start D2 D3 D4 D5 D6 E stop

efficiency = 7/10 scale factor for maximum bit rate

UART Implementations
oversampling at receiver

TX reg

TX

RX

in s-oversampling

RX reg

fT

1/s

fR

1/s

prescaler 1/C fclk,T

prescaler 1/C fclk,R

D0

D1

D2

D3

D4

D5

D6

1 s1 s

UART Implementations
clock generation in ATmega1280 (s = 2) s = 8 s = 16

UART implementations

How to obtain the bit value

Di

vs/2 vs/2+1 vs/2+2

val(Di) = maj(vs/2, vs/2+1, vs/2+2) stability to non perfectly matched sender & receiver clk frequencies However: larger D more likely frame error

UART implementations

Baud rate matching

consider a transmitter T: B and Bis = fclk,T / (sC) error[%] = 100(Bis /B 1)

But, how bad is error[%]?

Assume no glitches! fT = fclk,T / C fR = fclk,R / C What do we know about correctness of Dk?

UART implementations

Baud rate matching

How to minimize error? Do not use division when calculating UBRR, but round to nearest division!

UART implementations

Before something goes wrong

Dk D(k+1)

a slower receiver
vs/2 vs/2+1 vs/2+2
sample number sk + s/2 + 1

T(n) time when sample number n is taken T(sk + s/2 + 1) = T(1) + (sk + s/2) / fR T(k) time when bit k is transmitted (start) T(k) = k s / fT

T(1) in [0,1/ fR)

T(sk + s/2 + 1) < T(k+1)

UART implementations

Before something goes wrong

Dk D(k+1)

a faster receiver
vs/2 vs/2+1 vs/2+2
sample number sk + s/2 + 1

T(n) time when sample number n is taken T(sk + s/2 + 1) = T(1) + (sk + s/2) / fR T(k) time when bit k is transmitted (start) T(k) = k s / fT

T(1) in [0,1/ fR)

T(k) < T(sk + s/2 + 1)

UART implementations

k is correct, if and only if k s / fT < T(1) + (sk + s/2) / fR < (k+1) s / fT

Example. 7E1 k = 10 must be correct. Validate with formula above.

Physical backends

RS-232 (EIA-232)
single-ended, serial, point-to-point defines physical layer usage: mC PC mC mC over longer distances (>1m) connectors: 25 line 9 lines (D-SUB9) TXD, RXD, GND flow control electrical characteristics: sender +/- 3 -15 V receiver +/- 25 V

Physical backends

Example
MAX232
from [Texas Instruments]

Logical function is trivial Electrical characteristics works as a charge pump Sender: TTL [0,5] V [-15,+15] V Receiver: [-30,+30] V TTL

Physical backends

Example Application
MAX232 application C1, C2 needed by the charge pump

mC sender

PC receiver

Physical backends

RS-422 (EIA-422)
differential signalling for both TXD and RXD better in noisy environments higher transmission range higher data rates

= 1.2 km

from [1]

USART

restrictive B = f / (sC) but: need oversampling!

synchronous communication sender provides clock signal no (or less) oversampling necessary
TX CK RX CK

TX reg fT sender

RX reg

Q: still metastability problems?

receiver

USART Implementations
revisiting clock generation in ATmega1280 (s = 2) s = 8 s = 16

USART Implementations
USART clock generation in ATmega1280 s = 2 (s = 8) (s = 16)

sender: DDR_XCK = 1 receiver: DDR_XCK = 0

maximum baud rate B = fT / 4

USART Implementations
USART clock generation in ATmega1280 s = 2 (s = 8) (s = 16)

Sync Register: prevent from metastable clock

SPI

Serial Peripheral Interface (not Programming!) synchronous, p2p used for fast full duplex communication master multiple slaves very simple
MOSI M reg fT

MISO
SCK SS

S reg

& slave

master

SPI

Serial Peripheral Interface after 8 clks, M reg and S reg have been exchanged multiple SS, for different slaves, each

MOSI M reg fT

MISO SCK
SS

S reg

& slave

master

IC (IIC, TWI)

Inter-IC bus synchronous, bus, single ended, master-slave (even multiple master!) developed by Philips speed: standard mode 100 kbit/s fast mode 400 kbit/s high-speed mode 3.4 Mbit/s

co-existence possible

Vdd SDA Vdd SCL master

IC (IIC, TWI)

Bus need addresses and mutex on bus

Addresses 7 bit 0000XXX, 1111XXX reserved newer ones 10 bit 1st message 11111(A9)(A8)(R/W) 2nd message (A7) ... (A0) addresses partly programmable

IC

Special sequences Start

by master Start ... at start of packet

Ack

by slave by master

Ack ... after every transmitted Byte

Stop

Stop ... at end of packet

IC

Typical Transmission
master writes to slave master releases slave pulls down

st

ack

IC

Typical Transmission
slave writes to master slave releases master pulls down

by master st 1 0 1 0 0 0 0 0 nack (!)

IC

Typical Transmission
multiple Bytes & with address

7 bit address
(Start) (Address) (Ack) [(Byte k) (Ack)]n (Stop)
10 bit address (Start) (Address 1) (Ack) (Adress 2) (Ack) [(Byte k) (Ack)]n (Stop)

IC

Slow slave

st

0 master releases, but slave not

ack

slave releases

IC

Mutex
required because of multiple masters technique: - write - read back - compare makes use of the recessive state! Finally only one master will win (except for the case where they transmit identical data)

wireless communication

IEEE 802.15.1 (Bluetooth)

Wireless medium access control (MAC) and physical layer (PHY) specifications for wireless personal area networks (WPANs) master-slave

PHY: In unlicensed 2.4 GHz band Frequency hopping (pseudorandom) TDM to provide multiple top-level links Master hops, slaves synchronize and follow

wireless communication

Communication graph
only single master per net, all slaves synchronize to single master master maybe slave in other net multi hop

wireless communication

Core system
layered architecture

Logical Link Control and Adaptation Protocol

Link Manager Protocol controller Link Control Protocol Radio frequency protocol
from [3]

wireless communication

Core system
L2CAP provide QoS, optional Base Band resource manager Scheduler, access contracts Link controller en/decoding Messaging, flow control (ACK, )

wireless communication

Core system
Data transportation in frames of variable size (async or isochronous) synchronous links: periodic, reserved slots, fixed size packets in a stream (unframed) Fault Tolerance Baseband packets use forward error correction and CRC trigger retransmission broadcast links: simply send multiple times

wireless communication

packet

from [3]

0-2745 bit

wireless communication

packet

depends on packet type

here, asynchronous connection-oriented

wireless communication

PHY Protocol details master starts in slot in {0,2,4,} transmits packet over some time slots [maximum 5] (625 us) slave responds (not in case of broadcast) in slot in {1,3,5,...} Beacon train slots master transmits beacon parked slaves synchronize Modulation Gaussian frequency shift keying binary 1 = higher frequency, binary 0 = lower frequency 1Msymbol/s

wireless communication

Link Control Protocol details master slave communication

Retransmission
Master-slave retransmit if no ACK received Master broadcast retransmit a const number of times

wireless communication

Link Control Protocol details master slave communication

Inquiry scan device transmits inquiry REQ on random frequencies, waits for response

frequency hop sync

wireless communication

Link Manager Protocol additional flow control/ACK schemes, negotiate

from [3]

wireless communication

Example
LMX9830
National Semiconductor

from [5]

wireless communication

Another Example
IEEE 802.15.4 (ZigBee)

In RZ200: Atmel AT86RF230

from [4]

References

[1] Analog Devices, +5 V Powered RS-232/RS-422 Transceiver Manual http://www.analog.com/static/imported-files/data_sheets/AD7306.pdf [2] Steave Heath, Embedded Systems Design, 2nd edition. 2003 [3] IEEE 802.15.4 standard Wireless medium access control (MAC) and physical layer (PHY) specifications for wireless personal area networks (WPANs) http://standards.ieee.org/getieee802/802.15.html [4] Atmel Manual, http://www.atmel.com/dyn/resources/prod_documents/doc5131.pdf [5] National Semiconductor, LMX9830 Manual