Introduction: Counters

Counters are circuits that cycle through a specified

number of states.

Two types of counters:

synchronous (parallel) counters asynchronous (ripple) counters

Ripple counters allow some flip-flop outputs to be

used as a source of clock for other flip-flops.

Synchronous counters apply the same clock to all

flip-flops.

CS1104-13

Introduction: Counters

Asynchronous (Ripple) Counters

Asynchronous counters: the flip-flops do not change
states at exactly the same time as they do not have a common clock pulse.

Also known as ripple counters, as the input clock

pulse ripples through the counter cumulative delay is a drawback. MOD-x counter cycles through x states.)

n flip-flops a MOD (modulus) 2n counter. (Note: A

Output of the last flip-flop (MSB) divides the input
clock frequency by the MOD number of the counter, hence a counter is also a frequency divider.

CS1104-13

Asynchronous (Ripple) Counters

Asynchronous (Ripple) Counters

Example: 2-bit ripple binary counter. Output of one flip-flop is connected to the clock input
of the next more-significant flip-flop.
HIGH J CLK C K FF0 CLK Q0 Q0 0 Q1 0 CS1104-13 1 0 0 1 1 1 0 0 3 1 2 3 4 Q0 Q0 J C K FF1 Q1

Timing diagram 00 01 10 11 00 ...

Asynchronous (Ripple) Counters

Asynchronous (Ripple) Counters

Example: 3-bit ripple binary counter.
HIGH J CLK C K FF0 Q0 Q0 J C K Q1 Q1 J C K FF2 Q2

FF1

CLK Q0 Q1 Q2 0 0 0

1 1 0 0

2 0 1 0

3 1 1 0

4 0 0 1

5 1 0 1

6 0 1 1

7 1 1 1

8 0 0 0 Recycles back to 0

CS1104-13

Asynchronous (Ripple) Counters

Asynchronous (Ripple) Counters

Propagation delays in an asynchronous (rippleclocked) binary counter.

If the accumulated delay is greater than the clock

pulse, some counter states may be misrepresented!
CLK Q0 Q1 Q2 tPLH (CLK to Q0) 1 2 3 4

tPHL (CLK to Q0) tPLH (Q0 to Q1)

tPHL (CLK to Q0) tPHL (Q0 to Q1) tPLH (Q1 to Q2)

CS1104-13

Asynchronous (Ripple) Counters

Asynchronous (Ripple) Counters

Example: 4-bit ripple binary counter (negative-edge
triggered).
HIGH J CLK C K FF0 CLK 1 Q0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Q0 J C K FF1 Q1 J C K FF2 Q2 J C K FF3 Q3

Q1
Q2 Q3 CS1104-13 Asynchronous (Ripple) Counters 6

Asyn. Counters with MOD no. < 2

States may be skipped resulting in a truncated
sequence.

Technique: force counter to recycle before going

through all of the states in the binary sequence.

Example: Given the following circuit, determine the

counting sequence (and hence the modulus no.)
C
Q J

All J, K inputs are 1 (HIGH).

CLK K Q CLR

CLK K Q CLR

CLK K Q CLR

B C
Asynchronous Counters with MOD number < 2^n 7

CS1104-13

Asyn. Counters with MOD no. < 2

Example (contd):
C
Q J

All J, K inputs are 1 (HIGH).

CLK K Q CLR

CLK K Q CLR

CLK K Q CLR

B C
1 2 3 4 5 6 7 8 9 10 11 12

Clock A B C NAND 1 Output 0

CS1104-13

MOD-6 counter produced by clearing (a MOD-8 binary counter) when count of six (110) occurs.
8

Asynchronous Counters with MOD number < 2^n

Asyn. Counters with MOD no. < 2

CBA order).
1 2 3 4 5 6 7 8 9 10 11 12

Example (contd): Counting sequence of circuit (in

Clock A 0 1 0 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 0 0

B 0
C 0 NAND 1 Output 0

Temporary state

111

000 001

110 101 100

CS1104-13

010 011

Counter is a MOD-6 counter.

Asynchronous Counters with MOD number < 2^n

Asyn. Counters with MOD no. < 2

counter? MOD-7 counter? MOD-12 counter?

Exercise: How to construct an asynchronous MOD-5

Question: The following is a MOD-? counter?

F
Q Q J K CLR

Q Q

J K CLR

Q Q

J K CLR

Q Q

J K CLR

Q Q

J K CLR

Q Q

J K CLR

C D E F

All J = K = 1.

CS1104-13

Asynchronous Counters with MOD number < 2^n

10

Asyn. Counters with MOD no. < 2

Decade counters (or BCD counters) are counters

with 10 states (modulus-10) in their sequence. They are commonly used in daily life (e.g.: utility meters, odometers, etc.).

Design an asynchronous decade counter.

(A.C)' HIGH J CLK C K CLR Q D C B A

J C

J C

J C

K CLR

K CLR

K CLR

CS1104-13

Asynchronous Counters with MOD number < 2^n

11

Asyn. Counters with MOD no. < 2

Asynchronous decade/BCD counter (contd).
HIGH J CLK C K Q

J C K

J C K

J C K

(A.C)'

CLR

CLR

CLR

CLR

Clock D 0 C 0 B 0 A 0 NAND output

CS1104-13

1
1

2
0

3
1

4
0

5
1

6
0

7
1

8
0

9
1

10
0 0 0 0

11

0
0 0

1
0 0

1
0 0

0
1 0

0
1 0

1
1 0

1
1 0

0
0 1

0
0 1

Asynchronous Counters with MOD number < 2^n

12

Asynchronous Down Counters

Example: A 3-bit binary (MOD-8) down counter.
000
1 J CLK Q Q0 J Q Q1 J Q Q2

001 010 011

111
110 101

C Q' K

C K Q'

C K Q'

100
CLK Q0 Q1 Q2 0 0 0 1 1 1 1 2 0 1 1 3 1 0 1 4 0 0 1 5 1 1 0 6 0 1 0 7 1 0 0 8 0 0 0

CS1104-13

Asynchronous Down Counters

13

Synchronous (Parallel) Counters

Synchronous (parallel) counters: the flip-flops are
clocked at the same time by a common clock pulse.

We can design these counters using the sequential

logic design process (covered in Lecture #12).

Example: 2-bit synchronous binary counter (using T

flip-flops, or JK flip-flops with identical J,K inputs).
00 11 01 10
Present state Next state Flip-flop inputs

A1 A0 0 0 0 1 1 0 1 1

A1+ A0+ 0 1 1 0 1 1 0 0

TA1 TA0 0 1 1 1 0 1 1 1

CS1104-13

Synchronous (Parallel) Counters

14

Synchronous (Parallel) Counters

Example: 2-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J,K inputs).
Present state Next state Flip-flop inputs

A1 A0 0 0 0 1 1 0 1 1

A1+ A0+ 0 1 1 0 1 1 0 0
1

TA1 TA0 0 1 1 1 0 1 1 1

TA1 = A0 TA0 = 1

A0

A1

C Q' K CLK

C K Q'

CS1104-13

Synchronous (Parallel) Counters

15

Synchronous (Parallel) Counters

Example: 3-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J, K inputs).
Present state A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A1
1

A2+ 0 0 0 1 1 1 1 0

Next state A1+ A0+ 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0

1

Flip-flop inputs TA2 TA1 TA0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 A1

1 1 1 1 1 1 1

A1
1 1

A2 A0

A2

A2

A0

A0

TA2 = A1.A0
CS1104-13

TA1 = A0
Synchronous (Parallel) Counters

TA0 = 1
16

Synchronous (Parallel) Counters

Example: 3-bit synchronous binary counter (contd).
TA2 = A1.A0
A2

TA1 = A0
A1

TA0 = 1
A0

Q J K J

Q K J

Q K

CP 1

CS1104-13

Synchronous (Parallel) Counters

17

Synchronous (Parallel) Counters

Note that in a binary counter, the nth bit (shown
underlined) is always complemented whenever
01111 10000
or 11111 00000

Hence, Xn is complemented whenever

Xn-1Xn-2 ... X1X0 = 1111.

As a result, if T flip-flops are used, then

TXn = Xn-1 . Xn-2 . ... . X1 . X0

CS1104-13

Synchronous (Parallel) Counters

18

Synchronous (Parallel) Counters

Example: 4-bit synchronous binary counter.
TA3 = A2 . A1 . A0 TA2 = A1 . A0 TA1 = A0 TA0 = 1
1
J Q A0 J Q A1 A1.A0 J Q A2

A2.A1.A0
J Q A3

C Q' K CLK

C K Q'

C K Q'

C K Q'

CS1104-13

Synchronous (Parallel) Counters

19

Synchronous (Parallel) Counters

Example: Synchronous decade/BCD counter.
Clock pulse Initially 1 2 3 4 5 6 7 8 9 10 (recycle) Q3 0 0 0 0 0 0 0 0 1 1 0 Q2 0 0 0 0 1 1 1 1 0 0 0 Q1 0 0 1 1 0 0 1 1 0 0 0 Q0 0 1 0 1 0 1 0 1 0 1 0

T0 = 1 T1 = Q3'.Q0 T2 = Q1.Q0 T3 = Q2.Q1.Q0 + Q3.Q0

CS1104-13

Synchronous (Parallel) Counters

20

Synchronous (Parallel) Counters

Example: Synchronous decade/BCD counter
(contd).
T0 = 1 T1 = Q3'.Q0 T2 = Q1.Q0 T3 = Q2.Q1.Q0 + Q3.Q0
Q0 1 T C Q Q' T C Q Q' Q1 T C Q Q' Q2 T C Q Q' Q3

CLK

CS1104-13

Synchronous (Parallel) Counters

21

Up/Down Synchronous Counters

Up/down synchronous counter: a bidirectional
counter that is capable of counting either up or down.

An input (control) line Up/Down (or simply Up)

specifies the direction of counting.
Up/Down = 1 Count upward Up/Down = 0 Count downward

CS1104-13

Up/Down Synchronous Counters

22

Up/Down Synchronous Counters

Example: A 3-bit up/down synchronous binary
counter.
Clock pulse 0 1 2 3 4 5 6 7 Up Q2 0 0 0 0 1 1 1 1 Q1 0 0 1 1 0 0 1 1 Q0 0 1 0 1 0 1 0 1 Down

TQ0 = 1 TQ1 = (Q0.Up) + (Q0'.Up' ) TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )

CS1104-13

Up counter TQ0 = 1 TQ1 = Q0 TQ2 = Q0.Q1

Down counter TQ0 = 1 TQ1 = Q0 TQ2 = Q0.Q1

23

Up/Down Synchronous Counters

Up/Down Synchronous Counters

Example: A 3-bit up/down synchronous binary
counter (contd).
TQ0 = 1 TQ1 = (Q0.Up) + (Q0'.Up' ) TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )

Q0 1 Up T C Q Q' T C Q Q'

Q1 T C Q Q' Q2

CLK

CS1104-13

Up/Down Synchronous Counters

24

Designing Synchronous Counters

Covered in Lecture #12. Example: A 3-bit Gray code
counter (using JK flip-flops).
000
100 001

101
111 110 010

011

Present state Q2 Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
CS1104-13

Q2+ 0 0 1 0 0 1 1 1

Next state Q1+ 0 1 1 1 0 0 1 0

Q0+ 1 1 0 0 0 0 1 1

JQ2 KQ2 0 X 0 X 1 X 0 X X 1 X 0 X 0 X 0

Flip-flop inputs JQ1 KQ1 JQ0 KQ0 0 X 1 X 1 X X 0 X 0 0 X X 0 X 1 0 X 0 X 0 X X 1 X 0 1 X X 1 X 0

25

Designing Synchronous Counters

Designing Synchronous Counters

3-bit Gray code counter: flip-flop inputs.
Q2 Q1Q0
00 0 1 X X X 01 11 10 1 X

Q2

Q1Q0
00 0 1 01 11 1 X X 10 X X

Q2

Q1Q0
00 0 1 1 01 11 X X X X 10 1

JQ2 = Q1.Q0'
Q1Q0
00 0 X 01 11 X X 10 X

JQ1 = Q2'.Q0
Q1Q0
00 0 X 01 11 X 10

JQ0 = Q2.Q1 + Q2'.Q1' = (Q2 Q1)'

Q2 Q1Q0
00 0 X 01 11 1 10 X

Q2

Q2

1 1

1 X

1 X

KQ2 = Q1'.Q0'

KQ1 = Q2.Q0

KQ0 = Q2.Q1' + Q2'.Q1 = Q2 Q1

26

CS1104-13

Designing Synchronous Counters

Designing Synchronous Counters

3-bit Gray code counter: logic diagram.
JQ2 = Q1.Q0' KQ2 = Q1'.Q0' JQ1 = Q2'.Q0 KQ1 = Q2.Q0 JQ0 = (Q2 Q1)' KQ0 = Q2 Q1

J C

Q0

J C

Q1

J C

Q2 Q2 '

K Q' Q0 ' CLK

Q1 K Q' '

K Q'

CS1104-13

Designing Synchronous Counters

27

Introduction: Registers
An n-bit register has a group of n flip-flops and some
logic gates and is capable of storing n bits of information.

The flip-flops store the information while the gates

control when and how new information is transferred into the register.

Some functions of register:

retrieve data from register store/load new data into register (serial or parallel)

shift the data within register (left or right)

CS1104-13

Introduction: Registers

28

Simple Registers
No external gates. Example: A 4-bit register. A new 4-bit data is loaded
every clock cycle.
A3 A2 A1 A0

Q
D

Q
D

Q
D

Q
D

CP I3 I2 I1 I0

CS1104-13

Simple Registers

29

Registers With Parallel Load

Instead of loading the register at every clock pulse,
we may want to control when to load.

Loading a register: transfer new information into the

register. Requires a load control input.

Parallel loading: all bits are loaded simultaneously.

CS1104-13

Registers With Parallel Load

30

Registers With Parallel Load

Load I0 Load'.A0 + Load. I0
D Q

A0

D Q

A1

I1

D Q

A2

I2

D Q

A3

I3
CLK CLEAR
CS1104-13 Registers With Parallel Load 31

Using Registers to implement Sequential Circuits

A sequential circuit may consist of a register
(memory) and a combinational circuit.
Next-state value
Register Clock Inputs Combinational circuit Outputs

The external inputs and present states of the register

determine the next states of the register and the external outputs, through the combinational circuit.

The combinational circuit may be implemented by

any of the methods covered in MSI components and Programmable Logic Devices.
CS1104-13 Using Registers to implement Sequential Circuits 32

Shift Registers
Another function of a register, besides storage, is to
provide for data movements.

Each stage (flip-flop) in a shift register represents

one bit of storage, and the shifting capability of a register permits the movement of data from stage to stage within the register, or into or out of the register upon application of clock pulses.

CS1104-13

Shift Registers

33

Shift Registers
Basic data movement in shift registers (four bits are
used for illustration).
Data in Data out Data out Data in

(a) Serial in/shift right/serial out

Data in Data out Data in

(b) Serial in/shift left/serial out

Data in

Data out

(c) Parallel in/serial out

(d) Serial in/parallel out

Data out

(e) Parallel in / parallel out

(f) Rotate right
CS1104-13

(g) Rotate left

Shift Registers 34

Serial In/Serial Out Shift Registers

Accepts data serially one bit at a time and also
produces output serially.

Serial data input

D Q C

Q0

D Q C

Q1

D Q C

Q2

D Q C

Q3

Serial data output

CLK

CS1104-13

Serial In/Serial Out Shift Registers

35

Serial In/Serial Out Shift Registers

Application: Serial transfer of data from one register
to another.
SI Clock Shift control Shift register A CP SO SI Shift register B SO

Clock Shift control CP T1 Wordtime

T2

T3

T4

CS1104-13

Serial In/Serial Out Shift Registers

36

Serial In/Serial Out Shift Registers

Serial-transfer example.
Timing Pulse Initial value After T1 After T2 After T3 After T4 Shift register A 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 0 1 1 Shift register B 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 Serial output of B 0 1 0 0 1

CS1104-13

Serial In/Serial Out Shift Registers

37

Serial In/Parallel Out Shift Registers

Accepts data serially. Outputs of all stages are available simultaneously.
Data input D Q C D Q C D Q C D Q C

CLK
Q0 Q1 Q2 Q3

Data input

SRG 4

CLK

C
Q0 Q1 Q2 Q3

Logic symbol

CS1104-13

Serial In/Parallel Out Shift Registers

38

Parallel In/Serial Out Shift Registers

Bits are entered simultaneously, but output is serial.
Data input D0 SHIFT/LOAD D1 D2 D3

D Q C

Q0

D Q C

Q1

D Q C

Q2

Serial data D Q Q3 out C

CLK SHIFT.Q0 + SHIFT'.D1 CS1104-13 Parallel In/Serial Out Shift Registers 39

Parallel In/Serial Out Shift Registers

Bits are entered simultaneously, but output is serial.
Data in D0 D1 D2 D3

SHIFT/LOAD CLK C

SRG 4

Serial data out

Logic symbol

CS1104-13

Parallel In/Serial Out Shift Registers

40

Parallel In/Parallel Out Shift Registers

Simultaneous input and output of all data bits.
Parallel data inputs D0 D Q C D1 D Q C D2 D Q C D3 D Q C

CLK Q0 Q1 Q2 Q3

Parallel data outputs

CS1104-13

Parallel In/Parallel Out Shift Registers

41

Bidirectional Shift Registers

Data can be shifted either left or right, using a control
line RIGHT/LEFT (or simply RIGHT) to indicate the direction.
RIGHT/LEFT Serial data in

RIGHT.Q0 + RIGHT'.Q2

D Q C Q0

D Q C

Q1

D Q C

Q2

D Q C

Q3

CLK CS1104-13 Bidirectional Shift Registers 42

Shift Register Counters

Shift register counter: a shift register with the serial
output connected back to the serial input.

They are classified as counters because they give a

specified sequence of states.

Two common types: the Johnson counter and the

Ring counter.

CS1104-13

Shift Register Counters

43

Ring Counters
One flip-flop (stage) for each state in the sequence. The output of the last stage is connected to the D
input of the first stage.

An n-bit ring counter cycles through n states. No decoding gates are required, as there is an output
that corresponds to every state the counter is in.

CS1104-13

Ring Counters

44

Ring Counters
Example: A 6-bit (MOD-6) ring counter.
PRE
D Q

Q0

D Q

Q1

D Q

Q2

D Q

Q3

D Q

Q4

D Q

Q5

CLR CLK

Clock 0 1 2 3 4 5
CS1104-13

Q0 1 0 0 0 0 0

Q1 0 1 0 0 0 0

Q2 0 0 1 0 0 0

Q3 0 0 0 1 0 0

Q4 0 0 0 0 1 0

Q5 0 0 0 0 0 1

100000 000001 000010 000100

45

010000 001000

Ring Counters

Johnson Counters
The complement of the output of the last stage is
connected back to the D input of the first stage.

Also called the twisted-ring counter. Require fewer flip-flops than ring counters but more
flip-flops than binary counters.

An n-bit Johnson counter cycles through 2n states. Require more decoding circuitry than ring counter
but less than binary counters.

CS1104-13

Johnson Counters

46

Johnson Counters
Example: A 4-bit (MOD-8) Johnson counter.
D Q

Q0

D Q

Q1

D Q

Q2

D Q Q'

Q3'

CLR CLK

Clock 0 1 2 3 4 5 6 7
CS1104-13

Q0 0 1 1 1 1 0 0 0

Q1 0 0 1 1 1 1 0 0

Q2 0 0 0 1 1 1 1 0

Q3 0 0 0 0 1 1 1 1

0000 0001 0011 0111 1111

47

1000 1100 1110

Johnson Counters

Johnson Counters
Decoding logic for a 4-bit Johnson counter.
Clock 0 1 2 3 4 5 6 7 A 0 1 1 1 1 0 0 0 B 0 0 1 1 1 1 0 0 C 0 0 0 1 1 1 1 0 D 0 0 0 0 1 1 1 1
Decoding

A'.D' A.B' B.C' C.D' A.D A'.B B'.C C'.D

A' D'
A B'

State 0 State 1 State 2 State 3 State 4 State 5

48

B C'
C D' A D A' B

B' C C' D
CS1104-13

State 6 State 7
Johnson Counters

End of segment