Unit 3

Topics covered: Pipelining

Basic concepts
Speed of execution of programs can be improved in two ways:
Faster circuit technology to build the processor and the memory. Arrange the hardware so that a number of operations can be performed simultaneously. The number of operations performed per second is increased although the elapsed time needed to perform any one operation is not changed.

Pipelining is an effective way of organizing concurrent activity in a computer system to improve the speed of execution of programs.

Basic concepts (contd..)

Processor executes a program by fetching and executing instructions one after the other. This is known as sequential execution. If Fi refers to the fetch step, and Ei refers to the execution step of instruction Ii, then sequential execution looks like:
Time
1 2 3

What if the execution of one instruction is overlapped with the fetching of the next one?

Basic concepts (contd..)

Computer has two separate hardware units, one for fetching instructions and one for executing instructions. Instruction is fetched by instruction fetch unit and deposited in an intermediate buffer B1. Buffer enables the instruction execution unit to execute the instruction while the fetch unit is fetching the next instruction. Results of the execution are deposited in the destination location specified by the instruction.
Interstagebuffer B1 Instruction fetch unit Execution unit

Basic concepts (contd..)

Computer is controlled by a clock whose period is such that the fetch and execute steps of any instruction can be completed in one clock cycle. First clock cycle: - Fetch unit fetches an instruction I1 (F1) and stores it in B1. Second clock cycle: - Fetch unit fetches an instruction I2 (F2) , and execution unit executes instruction I1 (E1). Third clock cycle: - Fetch unit fetches an instruction I3 (F3), and execution unit executes instruction I2 (E2). Fourth clock cycle: - Execution unit executes instruction I3 (E3).
Clockcycle Instruction I1 I2 I3 F1 E1 F2 E2 F3 E3 1 2 3 4 Time

Basic concepts (contd..)

In each clock cycle, the fetch unit fetches the next instruction, while the execution unit executes the current instruction stored in the interstage buffer.

Fetch and the execute units can be kept busy all the time.

If this pattern of fetch and execute can be sustained for a long time, the completion rate of instruction execution will be twice that achievable by the sequential operation. Fetch and execute units constitute a two-stage pipeline.
Each stage performs one step in processing of an instruction. Interstage storage buffer holds the information that needs to be passed from the fetch stage to execute stage. New information gets loaded into the buffer every clock cycle.

Basic concepts (contd..)

Suppose the processing of an instruction is divided into four steps: F Fetch: Read the instruction from the memory. D Decode: Decode the instruction and fetch the source operands. E Execute: Perform the operation specified by the instruction. W Write: Store the result in the destination location. There are four distinct hardware units, for each one of the steps. Information is passed from one unit to the next through an interstage buffer. Three interstage buffers connecting four units. As an instruction progresses through the pipeline, the information needed by the downstream units must be passed along.
Interstageb uffers

F:Fetch instruction B1

D:Decode instruction andfetch operands B2

E:Execute operation B3

W:Write results

Basic concepts (contd..)

Time Clockcycle Instruction I1 I2 I3 I4 F1 D1 F2 E1 D2 F3 W1 E2 D3 F4 W2 E3 D4 W3 E4 W4 1 2 3 4 5 6 7

Clock cycle 1: F1 Clock cycle 2: D1, F2 Clock cycle 3: E1, D2, F3 Clock cycle 4: W1, E2, D3, F4 Clock cycle 5: W2, E3, D4 Clock cycle 6: W3, E3, D4 Clock cycle 7: W4
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Basic concepts (contd..)

Time Clockcycle Instruction I1 I2 I3 I4 F1 D1 F2 E1 D2 F3 W1 E2 D3 F4 W2 E3 D4 W3 E4 W4 1 2 3 4 5 6 7

During clock cycle #4: Buffer B1 holds instruction I3, which is being decoded by the instruction-decoding unit. Instruction I3 was fetched in cycle 3. Buffer B2 holds the source and destination operands for instruction I 2. It also holds the information needed for the Write step (W2) of instruction I2. This information will be passed to the stage W in the following clock cycle. Buffer B3 holds the results produced by the execution unit and the destination information for instruction I1.
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Role of cache memory

Each stage in the pipeline is expected to complete its operation in one clock cycle:
Clock period should be sufficient to complete the longest task. Units which complete the tasks early remain idle for the remaining clock period. Tasks being performed in different stages should require about the same amount of time for pipelining to be effective.

If instructions are to be fetched from the main memory, the instruction fetch stage would take as much as ten times greater than the other stage operations inside the processor. However, if instructions are to be fetched from the cache memory which is on the processor chip, the time required to fetch the instruction would be more or less similar to the time required for other basic operations.
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Completes an instruction each clock cycle Therefore, four times as fast as without pipeline as long as nothing takes more than one cycle But sometimes things take longer -- for example, most executes such as ADD take one clock, but suppose DIVIDE takes three

and other stages idle Write has nothing to write Decode cant use its out buffer Fetch cant use its out buffer

Pipeline performance
Potential increase in performance achieved by using pipelining is proportional to the number of pipeline stages.
For example, if the number of pipeline stages is 4, then the rate of instruction processing is 4 times that of sequential execution of instructions. Pipelining does not cause a single instruction to be executed faster, it is the throughput that increases.

This rate can be achieved only if the pipelined operation can be sustained without interruption through program instruction. If a pipelined operation cannot be sustained without interruption, the pipeline is said to stall. A condition that causes the pipeline to stall is called a hazard.
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Data hazard
A data hazard is a condition in which either the source or the destination operand is not available at the time expected in the pipeline . Execution of the instruction occurs in the E stage of the pipeline.
Execution of most arithmetic and logic operations would take only one clock cycle. However, some operations such as division would take more time to complete. For example, the operation specified in instruction I2 takes three cycles to complete from cycle 4 to cycle 6.
T ime Clockcycle Instruction I1 I2 I3 I4 F1 D1 F2 E1 D2 F3 W1 E2 D3 F4 W2 E3 D4 W3 E4 W4 1 2 3 4 5 6 7

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Data hazard (contd..)

Time Clockcycle Instruction I1 I2 I3 I4 F1 D1 F2 E1 D2 F3 W1 E2 D3 F4 W2 E3 D4 W3 E4 W4 1 2 3 4 5 6 7

Cycles 5 and 6, the Write stage is idle, because it has no data to work with. Information in buffer B2 must be retained till the execution of the instruction I 2 is complete. Stage 2, and by extension stage 1 cannot accept new instructions because the information in B1 cannot be overwritten. Steps D6 and F5 must be postponed. A data hazard is a condition in which either the source or the destination operand is not available at the time expected in the pipeline.
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Data Hazards

Situations that cause the pipeline to stall because data to be operated on is delayed

execute takes extra cycle, for example

Control or instruction hazard

Pipeline may be stalled because an instruction is not available at the expected time. For example, while fetching an instruction a cache miss may occur, and hence the instruction may have to be fetched from the main memory. Fetching the instruction from the main memory takes much longer than fetching the instruction from the cache. Thus, the fetch cycle of the instruction cannot be completed in one cycle. For example, the fetching of instruction I2 results in a cache miss. Thus, F2 takes 4 clock cycles instead of 1. Time
Clockcycle 1 2 3 4 5 6 7 8 9 Instruction I1 I2 I3 F1 D1 E1 F2 W1 D2 F3 E2 D3 W2 E3 W3

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An instruction hazard (or control hazard) has caused the pipeline to stall Instruction I2 not in the cache, required a main memory access

Control or instruction hazard (contd..)

Fetch operation for instruction I2 results in a cache miss, and the instruction fetch unit must fetch this instruction from the main memory. Suppose fetching instruction I2 from the main memory takes 4 clock cycles. Instruction I2 will be available in buffer B1 at the end of clock cycle 5. The pipeline resumes its normal operation at this point. Decode unit is idle in cycles 3 through 5. Execute unit is idle in cycles 4 through 6. Write unit is idle in cycles 5 through 7. Such idle periods are called as stalls or bubbles. Once created in one of the pipeline stages, a bubble moves downstream unit it reaches the last unit.
T ime Clockc ycle Stage F:Fetch D:Decode E:Execute W:Write F
1

F D

2 1

F D

3 2

idle E
1

idle idle W
1

idle idle idle

D E

3 2

idle idle

E W

3 2

idle

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Structural hazard
Two instructions require the use of a hardware resource at the same time. Most common case is in access to the memory:
One instruction needs to access the memory as part of the Execute or Write stage. Other instruction is being fetched. If instructions and data reside in the same cache unit, only one instruction can proceed and the other is delayed.

Many processors have separate data and instruction caches to avoid this delay. In general, structural hazards can be avoided by providing sufficient resources on the processor chip.

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Structural hazard (contd..)

Clockcycle Instruction I1 I2 I3 I4 I5 1 F1 2 D1 F2 3 E1 D2 F3 4 W1 E2 D3 F4 M2 E3 D4 F5 W2 (LoadX(R1),R2 5 6 7

W3 E4 D5

Memory address X+R1 is computed in step E2 in cycle 4, memory access takes place in cycle 5, operand read from the memory is written into register R2 in cycle 6. Execution of instruction I2 takes two clock cycles 4 and 5. In cycle 6, both instructions I2 and I3 require access to register file. Pipeline is stalled because the register file cannot handle two operations at once.
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I2 writing to register file

I3 must wait for register file

calculate the address

I5 fetch delayed I2 takes extra cycle for cache access as part of execution

Pipelining and performance

Pipelining does not cause an individual instruction to be executed faster, rather, it increases the throughput.

Throughput is defined as the rate at which instruction execution is completed.

When a hazard occurs, one of the stages in the pipeline cannot complete its operation in one clock cycle.

The pipeline stalls causing a degradation in performance.

Performance level of one instruction completion in each clock cycle is the upper limit for the throughput that can be achieved in a pipelined processor.

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Data hazards
Data hazard is a situation in which the pipeline is stalled because the data to be operated on are delayed. Consider two instructions: I1 : A = 3 + A I2 : B = 4 x A If A = 5, and I1 and I2 are executed sequentially, B=32. In a pipelined processor, the execution of I2 can begin before the execution of I1. The value of A used in the execution of I2 will be the original value of 5 leading to an incorrect result. Thus, instructions I1 and I2 depend on each other, because the data used by I 2 depends on the results generated by I1. Results obtained using sequential execution of instructions should be the same as the results obtained from pipelined execution. When two instructions depend on each other, they must be performed in the correct order.
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Concurrency
A B 3+ A 4 x A
Cant be performed concurrently--result incorrect if new value of A is not used

A B

5 x C 20 + C

Can be performed concurrently (or in either order) without affecting result

Concurrency
A B 3+ A 4 x A
Second operation depends on completion of first operation

A B

5 x C 20 + C

The two operations are independent

MUL R2, R3, R4 ADD R5, R4, R6 (dependent on result in R4 from previous instruction)

will write result in R4

cant finish decoding until result is in R4

Data hazards (contd..)

Clockcycle Instruction I1 I2 I3 I4 1 F1 2 D1 F2 3 E1 D2 F3 4 W1 5 6 7 8 9

Mul R2, R3, R4

D2A E2 D3 F4 W2 E3 D4

Add R5,R4,R6
W3 E4 W4

Mul instruction places the results of the multiply operation in register R4 at the end of clock cycle 4. Register R4 is used as a source operand in the Add instruction. Hence the Decode Unit decoding the Add instruction cannot proceed until the Write step of the first instruction is complete. Data dependency arises because the destination of one instruction is used as a source in the next instruction.
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Operand forwarding
Data hazard occurs because the destination of one instruction is used as the source in the next instruction. Hence, instruction I2 has to wait for the data to be written in the register file by the Write stage at the end of step W1. However, these data are available at the output of the ALU once the Execute stage completes step E1. Delay can be reduced or even eliminated if the result of instruction I1 can be forwarded directly for use in step E2. This is called operand forwarding.

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pipeline stall

data forwarding

MUL R2, R3, R4

R2, R3

R2 x R3 R4

R2 x R3 ADD R5, R4, R6 R5 R4 + R5

R6

R2 x R3

2 cycle stall introduced by hardware (if no data forwarding)

If solved by software: MUL R2, R3, R4 NOOP NOOP ADD R5, R4, R6

MUL R2, R3, R4

from R2

from R3

to R4

to I2

R2 x R3

Operand forwarding (contd..)

Source1 Source2

I1: Mul R2, R3, R4 I2: Add R5, R4, R6 Clock cycle 3: - Instruction I2 is decoded, and a data dependency is detected. - Operand not involved in the dependency, register R5 is loaded in register SRC1. Clock cycle 4: - Product produced by I1 is available in register RSLT. - The forwarding connection allows the result to be used in step E2. Instruction I2 proceeds without interruption.

SRC1

SRC2

Register file

ALU

RSLT Destination

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Handling data dependency in software

Data dependency may be detected by the hardware while decoding the instruction:

Detecting data dependencies and handling them can also be accomplished in software.

Control hardware may delay by an appropriate number of clock cycles reading of a register till its contents become available. The pipeline stalls for that many number of clock cycles.

Compiler can introduce the necessary delay by introducing an appropriate number of NOP instructions. For example, if a twocycle delay is needed between two instructions then two NOP instructions can be introduced between the two instructions. I1: Mul R2, R3, R4 NOP NOP I2: Add R5, R4, R6
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Side effects
Data dependencies are explicit easy to detect if a register specified as the destination in one instruction is used as a source in the subsequent instruction. However, some instructions also modify registers that are not specified as the destination.

For example, in the autoincrement and autodecrement addressing mode, the source register is modified as well.

When a location other than the one explicitly specified in the instruction as a destination location is affected, the instruction is said to have a side effect. Another example of a side effect is condition code flags which implicitly record the results of the previous instruction, and these results may be used in the subsequent instruction.
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Side effects (contd..)

I1: Add R3, R4 I2: AddWithCarry R2, R4 Instruction I1 sets the carry flag and instruction I2 uses the carry flag leading to an implicit dependency between the two instructions.

Instructions with side effects can lead to multiple data dependencies. Results in a significant increase in the complexity of hardware or software needed to handle the dependencies. Side effects should be kept to a minimum in instruction sets designed for execution on pipelined hardware.

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Instruction hazards
Instruction fetch units fetch instructions and supply the execution units with a steady stream of instructions. If the stream is interrupted then the pipeline stalls. Stream of instructions may be interrupted because of a cache miss or a branch instruction.

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Instruction hazards (contd..)

Consider a two-stage pipeline, first stage is the instruction fetch stage and the second stage is the instruction execute stage. Instructions I1, I2 and I3 are stored at successive memory locations. I2 is a branch instruction with branch target as instruction I k. I2 is an unconditional branch instruction. Clock cycle 3: - Fetch unit is fetching instruction I3. - Execute unit is decoding I2 and computing the branch target address. Clock cycle 4: - Processor must discard I3 which has been incorrectly fetched and fetch I k. - Execution unit is idle, and the pipeline stalls for one clock cycle.

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Instruction hazards (contd..)

Time Clockcycle Instruction I1 I2 (Branch) I3 Ik Ik+1 F1 E1 F2 E2 F3 X Executionunitidle 1 2 3 4 5 6

Fk

Ek Fk+1 Ek+ 1

Pipeline stalls for one clock cycle. Time lost as a result of a branch instruction is called as branch penalty. Branch penalty is one clock cycle.
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the lost cycle is the branch penalty

Instruction hazards (contd..)

Branch penalty depends on the length of the pipeline, may be higher for a longer pipeline. For a four-stage pipeline: - Branch target address is computed in stage E2. - Instructions I3 and I4 have to be discarded. - Execution unit is idle for 2 clock cycles. - Branch penalty is 2 clock cycles.
Clockcycle I1 I2 (Branch) I3 I4 Ik Ik+ 1 1 F1 2 D1 F2 3 E1 D2 F3 4 W1 E2 D3 F4 X X Fk Dk Fk+ 1 Ek Dk+ 1 Wk Ek+ 1 5 6 7 8 Time

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In a four stage pipeline, the penalty is two clock cycles

Instruction hazards (contd..)

Branch penalty can be reduced by computing the branch target address earlier in the pipeline. Instruction fetch unit has special hardware to identify a branch instruction after the instruction is fetched. Branch target address can be computed in the Decode stage (D2), rather than in the Execute stage (E2). Branch penalty is only one clock cycle.
Clockcycle I1 I2 (Branch) I3 Ik Ik+ 1 1 F1 2 D1 F2 3 E1 D2 F3 X Fk Dk Fk+ 1 Ek Wk 4 W1 5 6 7 Time

D k+ 1 E k+ 1

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Instruction hazards (contd..)

Instructionqueue F:Fetch instruction Instructionfetchunit

Queue can hold several instructions

Fetch unit fetches instructions before they are needed & stores them in a queue

D:Dispatch/ Decode unit

E:Execute instruction

W:Write results

Dispatch unit takes instructions from the front of the queue and dispatches them to the Execution unit. Dispatch unit also decodes the instruction.

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Instruction hazards (contd..)

Fetch unit must have sufficient decoding and processing capability to recognize and execute branch instructions. Pipeline stalls because of a data hazard:
Dispatch unit cannot issue instructions from the queue. Fetch unit continues to fetch instructions and add them to the queue.

Delay in fetching because of a cache miss or a branch:

Dispatch unit continues to dispatch instructions from the instruction queue.

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Instruction hazards (contd..)

Clockcycle Queuelength 1 1 F1 2 1 D1 F2 3 1 E1 D2 F3 F4 F5 D5 4 1 E1 5 2 E1 6 3 W1 E2 D3 W2 E3 D4 W3 E4 W4 7 2 8 1 9 1 10 1

I1 I2 I3 I4 I5 (Branch) I6 Ik Ik+ 1

Initial length of the queue is 1. Fetch adds 1 to the queue, dispatch reduces the length by 1. Queue length remains the same for first 4 clock cycles. I1 stalls the pipeline for 2 cycles. Queue has space, so the fetch unit continues and queue length rises to 3 in clock cycle 6.

I5 is a branch instruction with F6 X target instruction Ik. Ik is fetched in cycle 7, and I6 Fk Dk Ek Wk is discarded. Fk+1 D k+ 1 E k+ 1 However, this does not stall the pipeline, since I4 is dispatched. I2, I3, I4 and Ik are executed in successive clock cycles. Fetch unit computes the branch address concurrently with the execution of other instructions. This is called as branch folding.
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previous out, F1 in

F1 out, F2 in

F2 out, F3 in

F4 in

F5 in

instructions 3 and 4

instructions 3,4, and 5

keeps fetching despite stall

discards F6 and fetches K

calculates branch target concurrently branch folding

completes an instruction each clock cycle no branch penalty

Instruction hazards (contd..)

Branch folding can occur if there is at least one instruction available in the queue other than the branch instruction.

Instruction queue also mitigates the impact of cache misses:

In the event of a cache miss, the dispatch unit continues to send instructions to the execution unit as long as the queue is full. In the meantime, the desired cache block is read. If the queue does not become empty, cache miss has no effect on the rate of instruction execution.

Queue should ideally be full most of the time. Increasing the rate at which the fetch unit reads instructions from the cache. Most processors allow more than one instruction to be fetched from the cache in one clock cycle. Fetch unit must replenish the queue quickly after a branch has occurred.

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Conditional branches and branch prediction

Conditional branch instructions depend on the result of a preceding instruction.

Decision on whether to branch cannot be made until the execution of the preceding instruction is complete.

Branch instructions represent 20% of the dynamic instruction count of most programs.

Dynamic instruction count takes into consideration that some instructions are executed repeatedly.

Branch instructions may incur branch penalty reducing the performance gains expected from pipelining. Several techniques to mitigate the negative impact of branch penalty on performance.

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Delayed branch
Branch target address is computed in stage E2. Instructions I3 and I4 have to be discarded. Location following a branch instruction is called a branch delay slot. There may be more than one branch delay slot depending on the time it takes to determine whether the instruction is a branch instruction. In this case, there are two branch delay slots. The instructions in the delay slot are always fetched and at least partially executed before the branch decision is made and the branch address is computed.
Clockcycle I1 I2 (Branch) I3 I4 Ik Ik+ 1 1 F1 2 D1 F2 3 E1 D2 F3 4 W1 E2 D3 F4 X X Fk Dk Fk+ 1 Ek Dk+ 1 Wk Ek+ 1 5 6 7 8 Time

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if branch address calculated here

two branch delay slots

the penalty is two clock cycles in a four stage pipeline

fetched and decoded discarded

one branch delay slot

penalty reduced to one cycle

Delayed branch (contd..)

Delayed branching can minimize the penalty incurred as a result of conditional branch instructions. Since the instructions in the delay slots are always fetched and partially executed, it is better to arrange for them to be fully executed whether or not branch is taken.

If we are able to place useful instructions in these slots, then they will always be executed whether or not the branch is taken.

If we cannot place useful instructions in the branch delay slots, then we can fill these slots with NOP instructions.

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Delayed branch (contd..)

LOOP Shift_left Decrement Branch=0 Add (a)Originalprogramloop R1 R2 LOOP R1,R3

NEXT

LOOP

NEXT

Decrement Branch=0 Shift_left Add (b)Reorderedinstructions

R2 LOOP R1 R1,R3

Register R2 is used as a counter to determine how many times R1 is to be shifted. Processor has a two stage pipeline or one delay slot. Instructions can be reordered so that the shift left instruction appears in the delay slot. Shift left instruction is always executed whether the branch condition is true or false.

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Delayed branch (contd..)

Clockcycle Instruction Decrement F E 1 2 3 4 5 6 7 8 Time

Branch

Shift(delayslot)

Shift instruction is executed when the branch is taken.

E

Decrement(Branchtaken)

Branch

Shift(delayslot)

Shift instruction is executed when the branch is not taken.

E

Add(Branchnottaken)

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Delayed branch (contd..)

Logically, the program is executed as if the branch instruction were placed after the shift instruction. Branching takes place one instruction later than where the branch instruction appears in the instruction sequence (with reference to reordered instructions). Hence, this technique is termed as delayed branch. Delayed branch requires reordering as many instructions as the number of delay slots.
Usually possible to reorganize one instruction to fill one delay slot. Difficult to reorganize two or more instructions to fill two or more delay slots.

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Branch prediction
To reduce the branch penalty associated with conditional branches, we can predict whether the branch will be taken. Simplest form of branch prediction:
Assume that the branch will not take place. Continue to fetch instructions in sequential execution order. Until the branch condition is evaluated, instruction execution along the predicted path must be done on a speculative basis.

Speculative execution implies that the processor is executing instructions before it is certain that they are in the correct sequence.
Processor registers and memory locations should not be updated unless the sequence is confirmed. If the branch prediction turns out to be wrong, then instructions that were executed on a speculative basis and their data must be purged. Correct sequence of instructions must be fetched and executed.

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Branch prediction (contd..)

Time Clockcycle Instruction I1(Compare) I2(Branch>0) I3 I4 Ik F1 D1 F2 E1 D2 /P2 F3 W1 E2 D3 F4 X X Fk 1 2 3 4 5 6

I1 is a compare instruction and I2 is a branch instruction. Branch prediction takes place in cycle 3 when I2 is being decoded. I3 is being fetched at that time. Fetch unit predicts that the branch will not be taken and continues to fetch I4 in cycle 4 when I3 is being decoded.

Dk

Results of I1 are available in cycle 3. Fetch unit evaluates branch condition in cycle 4. If the branch prediction is incorrect, the fetch unit realizes at this point. I3 and I4 are discarded and Ik is fetched from the branch target address.
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Branch prediction (contd..)

Which way to predict the result of the branch instruction (taken or not taken) may be made in the hardware, depending on whether the target address of the branch instruction is lower or higher than the address of the branch instruction.
If the target address is lower, then the branch is predicted as taken. If the target address is higher, then the branch is predicted as not taken.

Branch prediction can also be handled by the compiler.

Complier can set the branch prediction bit to 0 or 1 to indicate the desired behavior. Instruction fetch unit checks the branch prediction bit to predict whether the branch will be taken.

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Branch prediction (contd..)

Branch prediction decision is the same every time an instruction is executed.

This is static branch prediction.

Branch prediction decision may change depending on the execution history.

This is dynamic branch prediction.

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Branch prediction (contd..)

Branch prediction algorithm may be described as a two-state machine with 2 states: LT : Branch is likely to be taken LNT: Branch is likely not to be taken Initial state of the machine be LNT When the branch instruction is executed, and if the branch is taken, the machine moves to state LT. If the branch is not taken, it remains in state LNT. When the same branch instruction is executed the next time, the branch is predicted as taken if the state of the machine is LT, else it is predicted as not taken.
Branchtaken(BT)

BNT

LNT

LT

BT

Branchnottaken(BNT)

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Branch prediction (contd..)

Requires only one bit of history information for each branch instruction. Works well inside loops:
Once a loop is entered, the branch instruction that controls the looping will always yield the same result until the last pass. In the last pass, the branch prediction will turn out to be incorrect. The branch history state machine will be changed to the opposite state. However, if the same loop is entered the next time, and there is more than one pass, the branch prediction machine will lead to wrong branch prediction.

Better performance may be achieved by keeping more execution history.

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Branch prediction (contd..)

BT

BNT

SNT BNT BNT BT

LNT

BT

LT BNT

ST BT

ST : Strong likely to be taken LT : Likely to be taken LNT : Likely not to be taken SNT : Strong likely not to be taken

Initial state of the algorithm is LNT. After the branch instruction is executed, if the branch is taken, the state is changed to ST For a branch instruction, the fetch unit predicts that the branch will be taken if the state is ST or LT, else it predicts that the branch will not be taken. In state SNT: - The prediction is that the branch is not taken. - If the branch is actually taken, the state changes to LNT. - Next time the branch is encountered, the prediction again is that it is not taken. - If the prediction is wrong the second time, the state changes to ST. - After that, the branch is predicted as taken.

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Branch prediction (contd..)

Consider a loop with a branch instruction at the end. Initial state of the branch prediction algorithm is LNT. In the first pass, the algorithm will predict that the branch is not taken.
This prediction will be incorrect. The state of the algorithm will change to ST.

In the subsequent passes, the algorithm will predict that the branch is taken:

Prediction will be incorrect, except for the last pass. The state will change to LT from ST.

In the last pass, the branch is not taken:

When the loop is entered the second time, the algorithm will predict that the branch is taken:

This prediction will be correct.

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Branch prediction (contd..)

Branch prediction algorithm mispredicts the outcome of the branch instruction in the first pass.
The prediction in the first pass depends on the initial state of the branch prediction algorithm. If the initial state can be set correctly, the misprediction in the first pass can be avoided.

Information necessary to set the initial state of the branch prediction algorithm can be provided by static prediction schemes.

With this, the only misprediction that occurs is on the final pass through the loop. This misprediction is unavoidable.

Comparing the branch target address with the address of the branch instruction, Checking the branch prediction bit set by the compiler. Branch instruction at the end of the loop, initial state is LT. Branch instruction at the start of the loop, initial state is LNT.

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Influence on Instruction Sets

Topics covered: Pipelining

Overview
Some instructions are much better suited to pipeline execution than others. Addressing modes Conditional code flags

Addressing Modes
Addressing modes include simple ones and complex ones. In choosing the addressing modes to be implemented in a pipelined processor, we must consider the effect of each addressing mode on instruction flow in the pipeline:

Side effects

The extent to which complex addressing modes cause the pipeline to stall Whether a given mode is likely to be used by compilers

Recall
Load X(R1), R2
Time Clockcycle Instruction I1 I2 (Load) I3 I4 F1 D1 F2 E1 D2 F3 W1 E2 D3 F4 M2 E3 D4 W2 W3 E4 1 2 3 4 5 6 7

I5

F5

D5

Load (R1), R2

Figure8.5.

EffectofaLoadinstructiononpipelinetiming.

Complex Addressing Mode

Load (X(R1)), R2

Clockcycle 1 Load F

2 D

3 X+ [R1]

6 W

Time

[X+[R1]] [[X+[R1]]] Forward

Nextinstruction

(a)Complexaddressingmode

Simple Addressing Mode

Add #X, R1, R2 Load (R2), R2 Load (R2), R2

Add

X+ [R1]

Load

[X+[R1]]

Load

[[X+[R1]]]

Nextinstruction

(b)Simpleaddressingmode

Addressing Modes

In a pipelined processor, complex addressing modes do not necessarily lead to faster execution. Advantage: reducing the number of instructions / program space Disadvantage: cause pipeline to stall / more hardware to decode / not convenient for compiler to work with Conclusion: complex addressing modes are not suitable for pipelined execution.

Addressing Modes
Good addressing modes should have:

Access to an operand does not require more than one access to the memory Only load and store instruction access memory operands The addressing modes used do not have side effects
Register, register indirect, index

Conditional Codes
If an optimizing compiler attempts to reorder instruction to avoid stalling the pipeline when branches or data dependencies between successive instructions occur, it must ensure that reordering does not cause a change in the outcome of a computation. The dependency introduced by the condition-code flags reduces the flexibility available for the compiler to reorder instructions.

Conditional Codes
Add Compare Branch=0 R1,R2 R3,R4 ...

(a)Aprogramfragment

Compare Add Branch=0

R3,R4 R1,R2 ...

(b)Instructionsreordered

Figure8.17.Instructionreordering.

Conditional Codes
Two conclusion:

To provide flexibility in reordering instructions, the condition-code flags should be affected by as few instruction as possible. The compiler should be able to specify in which instructions of a program the condition codes are affected and in which they are not.

Datapath and Control Considerations

Topics covered: Pipelining

Bus A

Bus B
In cremen t er

Bus C

PC

Regi s t er fi l e Co ns t an t4 MUX

A ALU B R

In st ru ct i on d ecod er

IR

MDR

MAR

Memoryb u s d at al i n es

Address l i nes

Figure 7.8.

Threeb usorganizationofthedatapath.

BusA

Pipelined Design
BusB

Register file

A ALU B R BusC PC IMAR Memoryaddress (Instructionfetches) MDR/Read Datacache

- Separate instruction and data caches - PC is connected to IMAR - DMAR - Separate MDR - Buffers for ALU - Instruction queue - Instruction decoder output

Controlsignalpipeline Incrementer

Instruction decoder

Instruction queue MDR/Write Instructioncache

DMAR Memoryaddress (Dataaccess)

- Reading an instruction from the instruction cache - Incrementing the PC - Decoding an instruction - Reading from or writing into the data cache - Reading the contents of up to two regs - Writing into one register in the reg file - Performing an ALU operation

Figure8.18. Datapathmodifiedforpipelinede xecution,with interstageb uffersattheinputandoutputoftheALU.

Superscalar Operation

Topics covered: Pipelining

Overview

The maximum throughput of a pipelined processor is one instruction per clock cycle. If we equip the processor with multiple processing units to handle several instructions in parallel in each processing stage, several instructions start execution in the same clock cycle multiple-issue. Processors are capable of achieving an instruction execution throughput of more than one instruction per cycle superscalar processors. Multiple-issue requires a wider path to the cache and multiple execution units.

Superscalar
F:Instruction fetchunit Instructionqueue

Floating point unit Dispatch unit Integer unit W:Write results

Figure8.19.

Aprocessorwithtwoexecutionunits.

Timing

Clockcycle I 1 (Fadd) I 2 (Add) I 3 (Fsub) I 4 (Sub)

1 F1 F2

2 D1 D2 F3 F4

3 E1A E2 D3 D4

4 E1B W2 E3 E4

5 E 1C

6 W1

Time

E3 W4

E3

W3

Figure8.20. AnexampleofinstructionexecutionflowintheprocessorofFigure8.19, assumingnohazardsareencountered.

Out-of-Order Execution

Hazards Exceptions Imprecise exceptions Precise exceptions

Clockcycle I 1 (Fadd) I 2 (Add) I 3 (Fsub) I 4 (Sub) 1 F1 F2 2 D1 D2 F3 F4 3 E1A E2 D3 D4 E3A E 3B 4 E 1B 5 E 1C 6 W1 W2 E 3C E4 W3 W4 7 Time

(a)Delayedwrite

Execution Completion
It is desirable to used out-of-order execution, so that an execution unit is freed to execute other instructions as soon as possible. At the same time, instructions must be completed in program order to allow precise exceptions. The use of temporary registers Commitment unit
Clockcycle I 1 (Fadd) I 2 (Add) I 3 (Fsub) I 4 (Sub) 1 F1 F2 2 D1 D2 F3 F4 3 E1A E2 D3 D4 4 E 1B TW2 E3A E4 E 3B TW4 5 E 1C 6 W1 W2 E 3C W3 W4 Time 7

(b)Usingtemporaryregisters

Performance Considerations

Topics covered: Pipelining

Overview

The execution time T of a program that has a dynamic instruction count N is given by:
T=

where S is the average number of clock cycles it takes to fetch and execute one instruction, and R is the clock rate. Instruction throughput is defined as the number of instructions executed per R second. P =
s

NS R

Overview

An n-stage pipeline has the potential to increase the throughput by n times. However, the only real measure of performance is the total execution time of a program. Higher instruction throughput will not necessarily lead to higher performance. Two questions regarding pipelining
How much of this potential increase in instruction throughput can be realized in practice? What is good value of n?

Number of Pipeline Stages

Since an n-stage pipeline has the potential to increase the throughput by n times, how about we use a 10,000-stage pipeline? As the number of stages increase, the probability of the pipeline being stalled increases. The inherent delay in the basic operations increases. Hardware considerations (area, power, complexity,)