Vous êtes sur la page 1sur 85

Chapter 6

Differential and Multistage Amplifiers


The most widely used circuit building block in analog integrated
circuits.

Use BJTs, MOSFETS and MESFETs (metal semiconductor FET
read 5.12 Gallium Arsenide-GaAs Device).
Differential pair circuits are one of the most
widely used circuit building blocks. The
input stage of every op amp is a differential
amplifier

Basic Characteristics
Two matched transistors with emitters
shorted together and connected to a
current source
Devices must always be in active mode
Amplifies the difference between the
two input voltages, but there is also a
common mode amplification in the non-
ideal case

Lets first understand how this circuit
works.
Assume the inputs are shorted together to a common
voltage, v
CM
, called the common mode voltage
equal currents flow through Q
1
and Q
2

emitter voltages equal and at v
CM
-0.7 in order
for the devices to be in active mode
collector currents are equal and so collector
voltages are also equal for equal load resistors
difference between collector voltages = 0
What happens when we vary v
CM
?
As long as devices in active mode, equal
currents flow through Q
1
and Q
2

Note: current through Q
1
and Q
2
always add up
to I, current through the current source
So, collector voltages do not change and
difference is still zero.
Differential pair circuits thus reject common
mode signals
Q
2
base grounded and Q
1
base at +1 V
All current flows through Q
1

No current flows through Q
2

Emitter voltage at 0.3V and Q
2
s EBJ not FB
v
C1
= V
CC
-oIR
C

v
C2
= V
CC

Q
2
base grounded and Q
1
base at -1 V
All current flows through Q
2

No current flows through Q
1

Emitter voltage at -0.7V and Q
1
s EBJ not
FB
v
C2
= V
CC
-aIR
C

v
C1
= V
CC

Apply a small signal v
i

Causes a small positive DI to flow in Q
1

Requires small negative DI in Q
2

since I
E1
+I
E2
= I
Can be used as a linear amplifier for small
signals (DI is a function of v
i
)
Differential pair responds to differences in the
input voltage
Can entirely steer current from one side of
the diff pair to the other with a relatively
small voltage
Lets now take a quantitative look at the large-
signal operation of the differential pair
Large-Signal Operation
First look at the emitter currents when the emitters are tied together




Some manipulations can lead to the following equations





and there is the constraint:





Given the exponential relationship, small differences in v
B1,2
can cause all of the
current to flow through one side
T
E B
V
V v
S
E
e
I
i

=
1
1
o
T
E B
V
V v
S
E
e
I
i

=
2
2
o
T
B B
V
v v
E
E
e
i
i
2 1
2
1

=
T
B B
V
v v
E E
E
e
i i
i
1 2
1
1
2 1
1

+
=
+
T
B B
V
v v
E E
E
e
i i
i
2 1
1
1
2 1
2

+
=
+
I i i
E E
= +
2 1
T
B B
V
v v
E
e
I
i
1 2
1
1

+
=
T
B B
V
v v
E
e
I
i
2 1
1
2

+
=
Notice v
B1
-v
B2
~= 4V
T
enough to switch all of current from one side to
the other
For small-signal analysis, we are interested in the region we can
approximate to be linear
small-signal condition: v
B1
-v
B2
< V
T
/2
Small-Signal Operation
Look at the small-signal operation: small
differential signal v
d
is applied









expand the exponential and keep the
first two terms
T
d
V
v
C
e
I
i

+
=
1
1
o
d B B
v v v =
2 1
T
d
T
d
T
d
V
v
V
v
V
v
C
e e
Ie
i
2 2
2
1

+
=
o
( )
( ) ( ) 2 2 2 2 1 2 1
2 1
1
d
T T d T d
T d
C
v
V
I I
V v V v
V v I
i
o o o
+ =
+ +
+
~
2 2 2
2
d
T
C
v
V
I I
i
o o
~
2 2
d
T
c
v
V
I
i
o
=
T T
C
m
V
I
V
I
g
2 o
= =
2
d m c
v g i =
multiply top
and bottom
by
T
d
V
v
e
2
Differential Voltage Gain
For small differential input signals, v
d
<< 2V
T
, the collector currents are









We can now find the differential gain to be
2
1
d
m C C
v
g I i + =
2
2
d
m C C
v
g I i =
( )
2
1
d
C m C C CC C
v
R g R I V v =
( )
2
2
d
C m C C CC C
v
R g R I V v + =
C m
d
c c
d
R g
v
v v
A =

=
2 1
Differential Half Circuit
We can break apart the differential pair circuit into two half circuits which
then looks like two common emitter circuits driven by +v
d
/2 and v
d
/2
We can then analyze the small-signal operation with the half
circuit, but must remember
parameters r
t
,g
m
, and r
o
are biased at I/2
input signal to the differential half circuit is v
d
/2
voltage gain of the differential amplifier (output taken
differentially) is equal to the voltage gain of the half circuit
( )
o C m
d
c
d
r R g
v
v
A = =
2
1
v
d
/2 r
t
v
t
g
m
v
t
r
o
R
C
v
c1
Common-Mode Gain
When we drive the differential pair with a common-mode signal,
v
CM
, the incremental resistance of the bias current effects circuit
operation and results in some gain (assumed to be 0 when R
was infinite)
R
R
v
r R
R
v v
C
CM
e
C
CM C
2 2
1
o o
~
+
=
R
R
v v
C
CM C
2
2
o
~
If the output is taken differentially, the output is zero since both sides move
together. However, if taken of the single circuit, the common-mode gain is finite


If we look at the differential gain of the circuit, we get


Then, the common rejection ratio (CMRR) will be



which is often expressed in dB
R
R
A
C
cm
2
o
=
C m d
R g A =
R g
A
A
CMRR
m
cm
d
2
1
~ =
cm
d
A
A
CMRR
10
log 20 =
CM and Differential Gain Equation
Input signals to a differential pair usually consists of two
components: common mode (v
CM
) and differential(v
d
)





Thus, the differential output signal will be in general
2
2 1
v v
v
CM
+
=
2 1
v v v
d
=
( )
2
2 1
2 1
v v
A v v A v
cm d o
+
+ =
The BJT Differential Pair
Use CD
Implemented by a
transistor circuit
Connection to RC not
essential to the operation
Essential that Q1
and Q2 never enter
saturation
Different Modes of Operation
Differential pair with a common-mode input
Common voltage

I/2

vE = vCM-VBE

vC1 = VCC ( ) o I RC

vC2 = VCC ( ) o I RC

vC1 vC2 = ?

Vary vCM (what happens?)

Rejects common-mode
Differential pair with a large differential input
Different Modes of Operation
vB1 = +1

Q1

Q2

vE = 0.3

Keeps Q2 off

vC1 = VCC - o I RC

vC2 = VCC
Differential pair with a large differential input o opposite polarity
To that of (b)
Different Modes of Operation
Differential pair with a small differential input
Different Modes of Operation
Exercise 6.1
5 0.7
1
4.3 = vE 0.7 :=
vC2 5 4.31 + := vC2 0.7 =
vC1 5 :=
Large-Signal Operation of the BJT Differential Pair
Equations
iE1
IS
o
e
vB1 vE ( )
VT

iE2
IS
o
e
vB2 vE ( )
VT

iE1
iE2
e
vB1 vB2 ( )
VT
iE1
iE1 iE2 +
1
1 e
vB2 vB1 ( )
VT
+
iE2
iE1 iE2 +
1
1 e
vB1 vB2 ( )
VT
+
iE1
1
1 e
vB2 vB1 ( )
VT
+
iE2
1
1 e
vB1 vB2 ( )
VT
+
Which can be manipulated to yield
iE1 iE2 + I
I
I
The collector
currents
can be obtained by
multiplying the
emitter currents by
Alfa, which is ver
close to unity
Large-Signal Operation of the BJT Differential Pair
Relatively small
difference voltage vB1
vB2 will cause the
current I to flow almost
entirely in one of the two
transistors.

4.VT (~100mV) is
sufficient to switch the
current to one side of the
pair.
Small-Signal Operation
The Collector Currents When vd is applied
vd vB1 vB2
iC1
o I
1 e
vd
VT
+
iC2
o I
1 e
vd
VT
+ iC1
o I e
vd
2 VT

e
vd
2 VT
e
vd
2 VT
+
vd
2 VT
iC1
o I 1
vd
2 VT
+
|

\
|
|
.

1
vd
2 VT
+ 1 +
vd
2 VT

iC1
o I 1
vd
2 VT
+
|

\
|
|
.

1
vd
2 VT
+ 1 +
vd
2 VT

~
iC2
o I
2
o I
2 VT
vd
2
iC1
o I
2
o I
2 VT
vd
2
+
vBQ1 VBE
vd
2
+ vBQ2 VBE
vd
2
gm
IC
VT
o I
2
VT
ic
Multiplying by
Assuming vd<<2VT
Interpretation: IC1 increases by ic and iC2 decreases by ic
An Alternative Viewpoint
re
VT
IE
VT
I
2
ie
vd
2 re
Assume I to be ideal its incremental resistance will be infinite and vd appears across a total
resistance 2.re.
ic o ie
o vd
2 re
gm
vd
2

A simple technique for


determining the signal currents
in a differential amplifier
excited by a differential voltage
signal v
d
; dc quantities are not
shown.
If emitter resistors are included
A differential amplifier with emitter resistances. Only signal quantities are shown (on color).
Input Differential Resistance
ib
ie
| 1 +
vd
2 re
| 1 +
Rid
vd
ib
| 1 +
( )
2 re
(
2 rt
This is the resistance-reflection rule; the resistance seen between the two bases is
equal to the total resistance in the emitter circuit multiplied by the beta+1
Input Differential Resistance
Differential Voltage Gain
iC1 IC gm
vd
2
+ iC2 IC gm
vd
2
IC
o I
2
vC1 VCC ICRC ( ) gm RC
vd
2

vC2 VCC ICRC ( ) gm RC
vd
2
+
Ad
vc1 vc2
vd
gm RC
Ad
o 2RC ( )
2 re 2 RE + ( )
RC
re RE +
Ad
o 2RC ( )
2 re 2 RE + ( )
RC
re RE +

The voltage gain is equal to the


ratio of the total resistance in the
collector circuit (2RC) to the total
resistance in the emitter circuit
(2re+2RE)
~
Equivalence of the differential amplifier (a) to the two common-emitter amplifiers in (b). This
equivalence applies only for differential input signals. Either of the two common-emitter
amplifiers in (b) can be used to evaluate the differential gain, input differential resistance,
frequency response, and so on, of the differential amplifier.

Equivalence of the Differential Amp. To a Common-Emitter Amp.
Differential amplifier fed in a
complementary manner
(push-pull or balanced)

Base of Q1 raised
Based of Q2 lowered
Equivalent Circuit Model of a Differential Half-Circuit
Ad gm
RC ro
RC ro +
|

\
|
|
.

Common-Mode Gain
vc1 vCM
o RC
2 R re +
vCM
o RC
2 R

vc2 vCM
o RC
2 R

Acm
o RC
2 R
Ad
1
2
gm RC
CMRR
Ad
Acm
Assuming symmetry
Acm
RC
2 R
ARC
RC
vCM
v1 v2 +
2
vo Ad v1 v2 ( ) Acm
v1 v2 +
2
|

\
|
|
.
+
If output is taken single-endedly
Acm and the differential gain Ad
We can define CMRR
CMRR gm R o 1
Common-mode
half-circuits
Assuming non-symmetry
Input Common-Mode Resistance
vCM
ro
Ricm =
Ricm
2 . Ricm
vCM
Equivalent common-mode half-circuit
Since the input common-mode resistance
is usually very large, its value will be
affected by the transistor resistances
R0 and r
Example 6.1 Class Discussion
Example 6.3
I 1 := VCC 15 := RC 10 := o 1 :=
vB1 t ( ) 5 0.005sin 2 t 1000 t ( ) + :=
vB2 t ( ) 5 0.005sin 2 t 1000 t ( ) := vBE 0.7 := at 1mA
a) vE b) gmc) iC d) vC e) vc1-vc2 f) gain at 1000Hz
a )
VBE 0.7 0.025ln
0.5
1
|

\
|
|
.
+ := VBE 0.683 =
vE 5 VBE := vE 4.317 =
b )
gm
IC
VT
:= gm 20 =
c )
iC1 t ( ) 0.5 gm 0.005sin 2 t 1000 t ( ) ( ) + := iC2 t ( ) 0.5 gm 0.005sin 2 t 1000 t ( ) ( ) :=
0 0.001 0.002 0.003 0.004 0.005
0.3
0.4
0.5
0.6
iC1 t ( )
iC2 t ( )
t
d )
vC1 t ( ) VCC ICRC ( ) 0.1RC sin 2 t 1000 t ( ) :=
vC2 t ( ) VCC ICRC ( ) 0.1RC sin 2 t 1000 t ( ) + :=
0 0.001 0.002 0.003 0.004 0.005
9
10
11
vC1 t ( )
vC2 t ( )
t
e )
0 0.001 0.002 0.003 0.004 0.005
2
0
2
vC2 t ( ) vC1 t ( )
t
Other Non-Ideal Characteristics


Input Offset Voltage




Input Bias and Offset Currents
Exercise 6.4
| 100 :=
Delt a_RC 0.02 := Delt a_IS 0.1 := Delt a_| 0.1 := I 100 := A
From Eq. 6.55
VOS VT
Delt a_RC
RC
|

\
|
|
.
2
Delt a_IS
IS
|

\
|
|
.
2
+
VOS 25 0.02 ( )
2
0.1
2
+ := VOS 2.55 =
IB
I
2 | 1 + ( )
:= IB 0.495 = A
IOS IB
Delt a_|
|
|

\
|
|
.
:= IOS 4.95 10
4
= 50nA
Biasing In BJT Integrated Circuits
Many resistors, transistors and capacitors makes impossible to use
conventional biasing methods

Biasing in IC is based on the use of constant-current sources

The Diode-Connected Transistor
i
i
| 1 +
|
| 1 +
i
Shorting the base and the collector of a BJT results in a two-
terminal device having an I-v characteristic identical ot the
iE-vBE of the BJT.

Since the BJT is still in active mode (vCB=0 results in an
active mode operation) the current I divides between base
and collector according to the value of the BJT Beta.

Thus, the BJT still operates as a transistor in the active mode.
This is the reason the I-v characteristics of the resulting
diode is identical to the iE-vBE relationship of the BJT
i
Exercise 6.5
R incremental = r t // (1/gm) // ro
Rinc
rt
1
gm

rt
1
gm
+
ro
rt
1
gm

rt
1
gm
+
ro +
rt
| 1 +
ro
rt
| 1 +
ro +
re ro
re ro +
re
Rinc
25
0.5
:=
Rinc 50 =
The Current Mirror
Io
I
O
|
| 1 +
I
E
I
REF
| 2 +
| 1 + ( )
I
E

I
O
I
REF
|
| 2 +
1
1
2
|
+
I
O
I
REF
1
2
|
+
1
V
O
V
EE
+ V
BE

VA
+
|

\
|
|
.
Finite Beta and Early Effect
For what value of | would
current mirror have a gain error
1%, 0.1 %

Imperfection due to base
current diverted from reference
current I
REF


Exercise 6.6
I
O5
1.073 10
3
= I
O5
I
O
5 4.3 ( )
Rout
+ := V
O
5 :=
at
I
O
9.804 10
4
= I
O
I
REF
1
2
|
+
:=
V
O
4.3 = V
O
V
EE
V
BE
+ := V
O
V
B
at
Rout 1 10
5
= Rout
100
I
REF
:=
Rout ro
VA
I
REF
I
REF
0.001 := | 100 := V
BE
0.7 := V
EE
5 :=
A Simple Current Source
I
REF
V
CC
V
BE

R
VCC
VBE
Neglecting the effect of finite beta and
Dependence of Io and Vo, the output
current Io will be equal IREF
Io IREF
Exercise 6.7
I
O
I
REF
I
REF
0.001 := V
CC
5 := V
BE
0.7 :=
neglect the ef f ects ro and f inite Beta
| 100 := V
A
50 :=
ro
V
A
I
REF
:= ro 5 10
4
=
R
V
CC
V
BE

I
REF
:= R 4.3 10
3
=
at
V
O
3 := I
O
I
REF
1
2
|
+
|

\
|
|
.
V
O
V
BE

ro
+ := I
O
1.026 10
3
=
Current-Steering Circuits
Generation of a number of cross currents.
I
REF
V
CC
V
EE
+ V
EB1
V
BE2

R
IC Circuits
2 power supplies
IREF is generated in the branch of
the diode-connected transistor Q1,
resistor R, and the diode-connected
transistor Q2.
Exercise 6.9
Comparison With MOS Circuits

1 - The MOS mirror does not suffer from the finite Beta
2 Ability to operate close to the power supply is an important issue on IC design
3 - Current Transfer: BJTs ~ relative areas; MOS ~ W/L
4 - VA lower for MOS

Improved Current-Source Circuits I
REF
|
| 1 +
2
| 1 + ( )
2
+

(
(

I
E

I
O
|
| 1 +
I
E

I
O
I
REF
1
1
2
|
2
| +
( )
+
1
1
2
|
2
+
I
REF
V
CC
V
EB1
V
BE3

R
The Wilson Current Mirror
Output resistance equal




A factor greater the then simple
Current source

Disadvantage: reduced output swing.
Observe that the voltage at the collector at
Q3 has to be greater than the negative
supply voltage by
(vBB1 = VCEsat-3), which is about a volt.

| ro
2
Exercise 6.10
I
E
I
E
I
E
| 1 +
I
E
| 1 +
2 I
E

| 1 +
| I
E

| 1 +
| I
E

| 1 +
| 2 +
| 1 +
I
E

| 2 +
| 1 + ( )
2
I
E

| | 2 + ( )
| 1 + ( )
2
I
E

~
I
REF
|
| 1 +
| 2 +
| 1 +
( )
2
+

(
(

I
E

I
O
| | 2 +
( )

| 1 +
( )
2
I
E

I
O
I
REF
| | 2 +
( )

(
| | 2 +
( )
| + 2 +
(
I
O
I
REF
1
1
2
|
2
+
Widlar Current Source
It differs from the basic current mirror in an
important way: a resistor RE is included in
the emitter lead of Q2. Neglecting the base
current we can write:
V
B1
V
T
ln
I
REF
I
S
|

\
|
|
.
V
B2
V
T
ln
I
O
I
S
|

\
|
|
.

V
B1
V
B2
V
T
ln
I
REF
I
O
|

\
|
|
.

V
B1
V
B2
I
O
R
E
+
I
O
R
E
V
T
ln
I
REF
I
O
|

\
|
|
.

Example 6.2
Example 6.3
Example 6.3
Current sources for biasing amplifying stages
Multistage Amplifiers Example 6.4 pg. 552
Calculating 1
st
stage gain
-- Assuming |=100
Model Eqs. on Pg. 263
e
r
In the same manor
O = =
+ =
k
r R
i
05 . 5 ) 25 101 ( 2
) 1 ( 2
2
t
|
5 4 2
t t
r r R
i
+ =
O = + =
k r r R
id
2 . 20
2 1 t t
O = =
+ = =
k
r r r
e
1 . 10 100 * 101
) )( 1 (
2 1
|
t t
O = = = =
100
25 .
25
2 1
E
T
I
V
e e
r r
) ( ) (
) (
1 +
= = =
|
|
| |
|
t
E
T
C
T
m I
V
I
V
g
r
Multistage Amplifiers Example 6.4 pg. 552
Calculating 1
st
stage gain
V
V
k k
r r
R R R
R I
R I
v
v
e e
i
R Total E E
R Total C C
id
o
A
4 . 22
200
40 || 05 . 5
) ||(
1
2 1
2 1 2
_ _
_ _
1
=
=
=
= =
O
O O
+
+

1
Ri2
Total emitter resistance
Total collector resistance
Multistage Amplifiers Example 6.4 pg. 552
Calculating 2
nd
stage gain
V
V
k k
r r
R R
e e
i
A 2 . 59
50
8 . 234 || 3
||
2
5 4
3 3
= = =
O
O O
+
Ri3
re4 and re5 calc. before
Potential gain is halved b/c converting to single-ended output
) )( 1 (
7 4 3 e i
r R R + + = |
O = = = 25
1
25
7
C
T
I
V
e
r
O =
O + O =
k
k R
i
8 . 234
) 25 3 . 2 ( 101
3
Multistage Amplifiers Example 6.4 pg. 552
Calculating 3
rd
stage gain
Purpose is to allow amplified
signal to swing negatively
Ri4
O = = 5
5
25
8 e
r
O = + =
+ + =
k
R r R
e i
5 . 303 ) 3000 5 ( 101
) )( 1 (
6 8 4
|
V
V
k
k k
R r
R R
v
v
e
i
o
o
A 24 . 6
325 . 2
5 . 303 || 7 . 15
||
3
4 7
4 5
2
3
= = = =
O
O O
+

Multistage Amplifiers Example 6.4 pg. 552


Calculating 3
rd
stage gain
V
V
R r
R
v
v
e o
o
A
998 .
3005
3000
4
6 8
6
3
= =
= =
+
Overall Gain
V
V
v
v
A A A A A
id
o
8513
4 3 2 1
= = =
O = + =
+
152 ) ( ||
1
8 6
5
|
R
e o
r R R
Output Resistance
The BJT Differential Amplifier With Active Load
v
o
g
m
v
d
R
o

R
o
r
o2
r
o4

r
o2
r
o4
+
r
o2
r
o4
r
o
R
o
r
o
2
v
o
g
m
v
d

r
o
2
|

\
|
|
.

v
o
v
d
g
m
r
o

2
g
m
I
C
V
T
r
o
V
A
I
C
I
C
I
2
g
m
r
o

V
A
V
T
constant f or a given transitor
R
i
2 r
t
G
m
g
m
I
2
V
T
The Cascode Configuration
The Cascode Configuration
BJT Single Stage Common-Emitter Amplifier
MOSFET Operation
MOS Differential Amplifiers MOS Differential Pair
MOS Differential Amplifiers Offset Voltage
MOS Differential Amplifiers Current Mirrors
Problem 6.1
RC 3000 := vBE 0.7 := iC 0.001 := vCM 2 := VCC 5 := | 100 :=
at iC 0.0005 := vBE 0.7 0.025ln
0.5
1
|

\
|
|
.
+ := vBE 0.683 =
vE vCM vBE := vE 2.683 =
iC1
|
| 1 +
iC := iC1 4.95 10
4
=
vC1 VCC iC1 RC := vC1 3.515 =
Problem 6.15
Ad 40 = Ad
vc2 vc1
vd
:=
vc2 2 = vc2 ie RC := vc1 2 = vc1 ie RC :=
iE2 6 10
4
= iE2 IE ie :=
iE1 1.4 10
3
= iE1 IE ie + :=
ie 4 10
4
= ie
vd
2 re RE + ( )
:=
RC 5000 := IE 0.001 := RE 100 := re 25 := vd 0.1 :=
BJT Differential Amplifier Laboratory

Purpose
The purpose of this lab is to investigate the behavior of a BJT difference amplifier. The circuits behavior needs to be
modeled with theoretical equations and a computer simulation. Comparison of laboratory results with theoretical and
simulated results is required for the relative validity of the models.

This lab also investigates the variation of differential and common mode gains using a Monte Carlo analysis.

Procedure
Construct the circuit in Figure 1 on PSpice and a Jameco JE26 Breadboard using a Hewlett-Packard 6205 Dual DC Power
Supply as the voltage sources and an MPQ2222 Bipolar Junction Transistor (Q2N2222).

Using a Keithley 169 Digital Multi-Meter measure the voltages across the resistors to determine the transistor base current
and collector current. From these current values calculate |.
Figure 1) Circuit for testing transistor | value
Next construct the amplifier
circuit shown in Figure 2.
All transistors are
MPQ2222 Bipolar Junction
Transistors. Use PSpice to
construct the circuit.
Measure the DC values at the
collector of Q1 and Q2. Do
the measured values agree
with theoretical ones.
Measure the DC value at the
emitter of Q1 and Q2. Do
the measured value agree
with the theoretical one.
Indicate the inverting and non-
inverting output.
Input an AC signal into Q1 of
your circuit at frequencies .
What is the single voltage
gain of your circuit?
Figure 2
Both inputs (Vin1 and Vin2) should be then grounded in order to determine the DC
operating point of the amplifier. Bias point voltages are measured and then compared to
the bias points produced by the PSpice simulation. Record DC bias point data.

Use a Wavetek 190 Function Generator with a sinusoidal input voltage of amplitude 0.031 V
and apply to one of the input terminals and the other terminal remained grounded, as shown
in figure 2. Use a Tektronix TDS 360 Digital Oscilloscope and a Fluke 1900A Multi-Meter the
output of the amplifier to observe input signal frequencies. Determine the corner frequency
(3-dB point) of the output and compared with the corner frequency generated with an AC
sweep in PSpice. Plot the PSpice AC sweep simulation.

Next calculate the differential mode voltage gain, A
V-dm
, from the laboratory data and
compare to the A
V-dm
predicted by the PSpice simulation and theoretical equations. Both
inputs are tied together to create a common mode signal on the input terminals. The output
voltage is then used to calculate the common mode voltage gain, A
V-cm
, and then compared
to the A
V-cm
predicted by the PSpice simulation and theoretical equations. From these
values the common mode rejection ratio (CMRR) should be calculated for each case.

Finally, PSpice should be used to perform a Monte Carlo analysis of the circuit. The
resistors were all given standard unbridged values and were allowed to vary uniformly
within 5% of the nominal resistor value. The transistors should be given a nominal | value
(say 175) and allowed to vary uniformly to +/- 100. The variations of differential and
common mode gains should be graphed on two histograms.

Analysis / Questions

What are the values of | for the first transistor?
(typical values of | range from approximately 125 to 225)

With the exception of the Monte Carlo analysis, all transistors were assumed to have this value in the
PSpice simulations. All four transistors were contained within one integrated circuit so that hopefully there
would be little change in | values from one transistor to the next, making the previous assumption
reasonably valid.

How close are the measured DC bias points of the circuit to those predicted by the PSpice simulation?

What is the reason for the small differences between measured and predicted voltages?

Exercises 6.17
An Active-Loaded CMOS Amplifier

Exercise 6.19
BiCMOS Amplifiers

Exercise 6.20
BiCMOS Amplifiers

Exercise 6.21
BiCMOS Amplifiers

Exercise 6.22
BiCMOS Current Mirrors and Differential Amplifiers
Gallium Arsenide (GaAs) Amplifiers

Current sources Exercise 6.23
Gallium Arsenide (GaAs) Amplifiers

A Cascode Current Source Exercise 6.24
Gallium Arsenide (GaAs) Amplifiers

Increasing The Output Resistance by Bootstrapping
Gallium Arsenide (GaAs) Amplifiers

A Simple Cascode Configuration The Composite Transistor
Gallium Arsenide (GaAs) Amplifiers

Differential Amplifiers
Multistage Amplifiers

Example 6.4
Multistage Amplifiers

Example 6.5 SPICE Simulation of a Multistage Amplifier