A Presentation on

Presented by Sneha T (09501A1951)

Beyond Moores Law

The number of transistors that Can be placed onto a Silicon-chip of a given size doubles every 18 months

The Moores graph

Definition
A chip in three-dimensional integrated circuit (3D-IC) technology is composed of two or more layers of active electronic components, integrated both vertically and horizontally into a single circuit.

Why 3D IC ?
The large growth of computer and information technology industry is depending on VLSI circuits with increasing functionality and performance at minimum cost and power dissipation and 2D ICs generate various gate delays and interconnection delay. So to reduce these delays and total power consumption, 3D IC technology is introduced.

2D vs 3D
Metric Total Area (mm2) 2D 31.36 3D 23.4 Change -25.3%

Total Wire Length (m)

Max Speed (Mhz) Power @ 63.7MHz (mW)

19.107
63.7 340.0

8.238
79.4 324.9

-56.9%
+24.6% -4.4%

FFT Logic Energy (J)

3.552

3.366

-5.2%

The evolution of 3D ICs

Compared to 2D and 2.5D ICs

Less interconnect wires Low power consumption High speed Less area HP LP SR GR

HP- high performance,LP-low power SR-special ram,GR-general ram

Architecture of 3D IC

What does it say

3D IC is a concept that can significantly : Improve interconnect performance, Increase transistor packing density, Reduce chip area Power dissipation
In 3D design structure the entire chip Si is divided by number of layers of oxide and metal, to form transistors.

Manufacturing Technologies
There are four ways to built 3D IC Monolithic Wafer on wafer Die on wafer Die on die

Monolithic
Electronic components and their connections (wiring) are built in layers on a single semiconductor wafer, which is then diced into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or throughsilicon vias.

Wafer on Wafer
Electronic components are built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D ICs.

Die on Wafer
Electronic components are built on two semiconductor wafers. One wafer is diced aligned and bonded onto die sites of the second wafer.

Die on Die
Electronic components are built on multiple dice, which are then aligned and bonded. One advantage of die-on-die is that each component die can be tested first, so that one bad die does not ruin an entire stack

Packing
Saves space by stacking separate chips into a single package This packaging, known as system in package (SIP) or chip stack MCM, don't integrate chips into a single circuit Communicate using off-chip signaling

Simulation
IntSim is an open-source CAD tool to simulate 2D and 3D-ICs. It can be used for predicting 2D/3D chip power, die size, number of metal levels and optimal sizes of metal levels based on various technology and design parameters. HeatWave is a commercial CAD tool to simulate whole-chip temperature down to the device level.

Performance Characteristics
TIMING ENERGY
With shorter interconnects in 3D ICs, both switching energy and cycle time are expected to be reduced

Timing Performance
The graph shows the results of a reduction in wire length due to 3D routing. Reduction in the interconnect lengths reduces RC delays and increase chip timing performance

Energy Performance
The graph shows the reduction in a normalized energy consumption with number of wire layers.

Benefits
Foot Print Cost Heterogeneous Integration Shorter Interconnect Power Design Circuit Security Bandwidth

Advantages
3D integration can reduce the wiring, thereby reducing the capacitances, power dissipation and chip area improves performance. Digital , analog circuits can be formed with better noise performance. Reduced interconnect delays(R,L,C) and high clock rates High integration density (may go heterogeneous) High band width -processors and advanced focal planes The cost of a 3-D IC will be 10 times less than the present ones.

Concerns In 3D Circuit
Thermal Issues in 3D-circuits Reliability Issues

Conclusion
3D ICs will be the first of a new generation of dense, inexpensive chips having less delay and interconnection losses that will replace the conventional storage and recording media.