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Complicated process due to following reasons: The High speeds at which ATM switches operate (few Mbps to few hundred Gbps), The large no. of inputs (~1000) that ATM switches must support. The variety of data rates that ATM switches support, The traffic management features that ATM switches support. The function of an ATM switch is divided according to three
Old values of the VPI/VCI are then replaced by the new values. A routing tag is attached to the cell which contains information
fetched from translation table. A multicast cell may carry a bit-map corresponding to the set of outlets for which cell is destined.
The cell is then forwarded to the switching fabric. Verifies HEC value of every cell & discards erroneous cells. Discards empty cells.
cells forwarded to CAC module and OAM cell to management one). Performs usage parameter control and network parameter control (UPC/NPC) at ingress point of network.
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modules. Buffers excess cells. Multicasting/broadcasting cells. Providing support for fault tolerance. Traffic concentration and multiplexing. Traffic expansion and de-multiplexing. Congestion notification.
(cell rate decoupling). Converts electrical signals into optical signals (SONET/SDH). Multiplexes user cells from signaling and OAM cells.
of switched virtual circuits. All control plane functions are performed by exchanging signaling messages. ATM switch forwards all the signaling cells received to CAC module. CAC module processes every connection request, and depending upon the availability of resources, determines new connections can be accepted or not.
cells.
SYSTEM SWITCH (PARIS - Shared medium Architecture) KNOCKOUT SWITCH (Multistage switch) MOONSHINE SWITCH (Improved Knockout)
PRELUDE SWITCH
Designed by CNET in France. Aimed at providing high-throughput and flexible switching
capability. Throughput is required to support high bandwidth applications like video. The flexibility is required to provide a multi-service environment that is capable of supporting different applications including video, voice and data. The prototype built supported a packet size of 16 bytes, 15 bytes payload and 1 byte header. Assumption is that the no. of input ports and output ports is equal to the no. of bytes in the packet (i.e. 16). Here we have assumed packet size of 4 bytes (3 payload, 1 header).
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4 stages: Framing and Parallelization (Stage 1): Packets converted from serial to parallel form. This state delivers a cell stream byte-by-byte without any phase relationship between one output to another. Clock Adaption and Phase alignment (Stage 2): Clocks are delivered from remote clock, so output ports operate based on these remote clocks. Locks the clock and phase of each cell carrier on all outputs to a central clock. Time shifts the packet by one byte from one link to next, resulting in a diagonal alignment. Ensures if header of a cell on output link in one cycle, then in next cycle the header is on next output link.
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Super-multiplexing Stage (Stage 3): Diagonally aligned packets are then fed into this stage. Extracts header information from all incoming packets and put it onto the first output that leads to the controller. The payloads are multiplexed onto the remaining output lines. Controller processes the headers and determines output port of the packet using address translation table.
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Demultiplexing and serialization (Stage 4): New header along with payload octet is stored in shared memory. Reassembles payloads from different output lines to form a 16-byte packet. Packets are then converted from parallel form to serial form.
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