ECE4112 Chap 6

Introduction to Chapter 6
Digital circuits are frequently used for arithmetic operations Fundamental arithmetic operations on binary numbers and digital circuits which perform arithmetic operations will be examined. HDL will be used to describe arithmetic circuits.
Ronald Tocci/Neal Widmer/Gregory Moss Digital Systems: Principles and Applications, 10e
Copyright 2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved...
6-9 Arithmetic Circuits
An arithmetic/logic unit (ALU) accepts data stored in memory and executes arithmetic and logic operations as instructed by the control unit.
Copyright 2007 by Pearson Education, Inc. Columbus, OH 43235 All rights reserved..
6-9 Arithmetic Circuits
Typical sequence of operations:
Control unit is instructed to add a specific number from a memory location to a number stored in the accumulator register. The number is transferred from memory to the B register. Number in B register and accumulator register are added in the logic circuit, with sum sent to accumulator for storage. The new number remains in the accumulator for further operations or can be transferred to memory for storage.
6-10 Parallel Binary Adder
The A and B variables represent 2 binary numbers to be added. The C variables are the carries. The S variables are the sum bits.
6-11 Design of a Full Adder
Construct a truth table of 3 inputs (2 numbers to be added and carry in) and 2 outputs (sum and carry out). Use algebraic methods or K-maps to simplify the resulting SOP form. The result is the logic circuit shown in Figure 6-7. The design process for a half adder is similar, but there is no carry in so there will be only 2 input bits.
Truth table for a full-adder circuit.
K maps for the full-adder outputs.
Circuitry for a full adder
6-12 Complete Parallel Adder With Registers
Register notation to indicate the contents of a register we use brackets:

[A]=1011 is the same as A3=1, A2=0, A1=1, A0=1
A transfer of data to or from a register is indicated with an arrow [B][A] means the contents of register B have been transferred to register A. This is a common form of notation and is also found in HDL.
6-12 Complete Parallel Adder With Registers
The following describes adding binary 1001 and 0101 using the parallel adder: A CLR pulse is applied at t1 The first binary number 1001 is transferred from memory to the B register at t2 The sum of 1001 and 0000 is transferred to the A register at t3 0101 is loaded from memory to the B register at t4 The sum outputs are transferred to the A register at t5 The sum of the two numbers is now present in the accumulator.
6-13 Carry Propagation

Parallel adder speed is limited by carry propagation (also called carry ripple). Carry propagation results from having to wait for the carry bits to ripple through the device. Additional bits will introduce more delay. Various techniques have been developed to reduce the delay. The look-ahead carry scheme is commonly used in high speed devices.
Design a carry look-ahead adder
Instead of waiting for C1, produce it directly
6-14 Integrated Circuit Parallel Adder
The most common parallel adder is a 4 bit device with 4 interconnected FAs and look-ahead Carry circuits. The A and B lines each represent 4 bit numbers to be added. The C0 is the carry in, the C4 is the carry out, and the lines are the sum of the two numbers.
6-14 Integrated Circuit Parallel Adder
Parallel adders may be cascaded together as shown to add larger numbers, in this case two 8 bit numbers.
N-bit operands result in N sum outputs and 1 carry output.
6-15 2s Complement System
Addition of negative and positive numbers using adders is done by placing the negative number into 2s complement form and performing normal addition. Subtraction is done by converting the number to be subtracted (subtrahend) to 2s complement and adding to the minuend. An adder can be used to perform addition and subtraction by designing a way to take the 2s complement for subtraction as described in Figure 6-13. To calculate the 2s complement, read a binary number from right to left and complement all bits after the first 1.
Parallel adder used to add and subtract numbers in 2scomplement system.
2s Complement Addition using 1s Complement Operands

Parallel adder used to perform subtraction (A B) using the 2s-complement system. The bits of the subtrahend (B) are inverted (1s complement), and C0 = 1 to produce the 2s complement
Parallel adder/subtractor using the 2s-complement system
ADD = 1, SUB = 0: B register passes to adder and Carry in = 0
ADD = 0, SUB = 1: Complement of B register passes to adder and Carry in = 1
6-16 ALU Integrated Circuits
ALUs can perform different arithmetic and logic functions as determined by a binary code on the function select inputs. There are many different devices. The 74LS382 (TTL) and HC382 (CMOS) is a typical device with 8 possible functions.
6-16 ALU Integrated Circuits
Two 74HC382 ALU chips connected as an eightbit adder
Prob. 6.22 Find the minimum time between the PGT of LOAD and PGT of TRANSFER for proper operation
Complete four-bit parallel adder with registers: tplh=tphl = 30 ns, ts=10ns, and the FA tp = 40ns.
Prob 6-40 Declare [a] and [b] 8-bit inputs and [z] output in VHDL
Prob 6-42 Given [a] = 10010111, [b] = 00101100. What is the value of the following.
Prob 6-44 Shift bits in [a] one bit to the right. The LSB should move to the MSB position.
Single-bit full adder in VHDL
4-bit VHDL adder
c is an intermediate signal: the carry bits
6.53 For a 4-bit adder, design a circuit that will set the following flags on the transfer pulse: S (sign), Z(zero), and C (carry)
Zero flag: 1 when all four inputs are 0
Sign flag: 1 when S3 = 1
Carry flag: 1 when C4 (output carry) = 1
6.23 Design an overflow circuit

Condition for overflow: Both numbers being added are positive and the resulting sign-bit is negative. Both numbers being added are negative and the resulting sign-bit is positive.
6.49 Modify the adder in Fig. 6.22 to operate on 12 bits

ECE4112 Chap 6

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ECE4112 Chap 6

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Introduction to Chapter 6

6-9 Arithmetic Circuits

6-9 Arithmetic Circuits

Typical sequence of operations:

6-10 Parallel Binary Adder

6-11 Design of a Full Adder

Truth table for a full-adder circuit.

K maps for the full-adder outputs.

Circuitry for a full adder

6-12 Complete Parallel Adder With Registers

Register notation to indicate the contents of a register we use brackets:

6-12 Complete Parallel Adder With Registers

6-13 Carry Propagation

Design a carry look-ahead adder

Instead of waiting for C1, produce it directly

6-14 Integrated Circuit Parallel Adder

6-14 Integrated Circuit Parallel Adder

N-bit operands result in N sum outputs and 1 carry output.

6-15 2s Complement System

Parallel adder used to add and subtract numbers in 2scomplement system.

2s Complement Addition using 1s Complement Operands

Parallel adder/subtractor using the 2s-complement system

ADD = 1, SUB = 0: B register passes to adder and Carry in = 0

ADD = 0, SUB = 1: Complement of B register passes to adder and Carry in = 1

6-16 ALU Integrated Circuits

6-16 ALU Integrated Circuits

Two 74HC382 ALU chips connected as an eightbit adder

Single-bit full adder in VHDL

4-bit VHDL adder

c is an intermediate signal: the carry bits

Zero flag: 1 when all four inputs are 0

Sign flag: 1 when S3 = 1

Carry flag: 1 when C4 (output carry) = 1

6.23 Design an overflow circuit

6.49 Modify the adder in Fig. 6.22 to operate on 12 bits

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