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Transistor Definitions
MOS - Metal Oxide Semiconductor FET - Field Effect Transistor BJT - Bipolar Junction Transistor
body
base
gate
source
n-channel MOSFET
BJT Symbols
collector collector
base
base
emitter
MOSFET Symbols
drain
gate source or drain body source A. n-channel MOSFET drain
body
gate
body
A circle is sometimes used on the gate terminal to show active low input
source
or drain
gate
gate source
body
B. p-channel MOSFET
Basic MOSFET
CMOS Inverter
VDD
A
n
Y = A'
GND
A
B
Y=A+B
A
B Y=AB
Y=AB
Note that we have not gone into all of the details of CMOS gate construction here. For example, to avoid damage caused by static electricity, different manufacturers developed a number of input protection circuits, to prevent input voltages from becoming too high. However, these protection circuits do not affect the logical behavior of the gates, so we will not go into the details here. This is not strictly true for most CMOS devices for applications that are power-switched; special inputs are required for power-off isolation between circuits.
Decoders
Decoder Fundamentals
Route data to one specific output line. Selection of devices, resources Code conversions. Arbitrary switching functions
implements the AND plane
Asserts one-of-many signal; at most one output will be asserted for any input combination
Encoding
Decimal 0 1 2 3 Unencoded 0001 0010 0100 1000
Binary Encoded 00 01 10 11
Note: Finite state machines may be unencoded ("one-hot") or binary encoded. If the all 0's state is used, then one less bit is needed and it is called modified one-hot coding.
Log2(N)
2:4 Decoder
A B A B A B
AND 2
EQ3
11 10 01 00
AND 2 A
EQ2
AND 2 A
EQ1
D0 D1
A B
AND 2 B
EQ0
EQ3
11 10 01 00
EQ2
EQ1
D0 D1 ENABLE
A B C
AND 3 B
EQ0
Static Hazards
Static Hazard
A
A B Y X1 A B Y
S B
A B
X2
Static Hazard
A
A B
In real circuits, delays don't exactly match; Added delay for illustration
AND 2
Y X1
A B
OR 2
S B
BUFF
S DA
B
AND 2 A
Y X2
Static Hazard
Static Hazard
AB 00 S=0 S=1 0 0 01 1 0 11 1 1 10 0
Illustrating the minimized function on a Karnaugh map. Only two 2-input AND gates are needed for the product terms
Static Hazard
AB 00 0 0 0 01 1 0 11 1 1 10 0
S
1
The blue oval shows the redundant term used to cover the transition between product terms.
Static Hazard
A
A B
AND 2
Y X1
S B
BUFF
S DA
B A B
AND 2 A
Y X2
A B C
OR 3
AND 2
Y X3
Static Hazard
D Q DFC1B CLK CLR A B Y C AND 4 D TCNT
CLDCK
ACLR
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Static Hazard
Flight Design Example
D DF1 CLK Q
DF1
CLK VCC Y D0 D1 D2 D3 Y
S1 S0
D DF1 CLK
D DF1 A Y CLK
TMR Triplet
GND
Majority Voter
High-skew buffer
Static Hazard
Flight Design Example
Care is needed when using TMR circuits. First, the output of the voter may be susceptible to a logic hazard glitch. This is not a problem if the TMR is feeding the input of another synchronous input. However, the TMR output should never feed asynchronous inputs such as flip-flop clocks, clears, sets, read/write inputs, etc.
Design Techniques for Radiation-Hardened FPGAs Actel Corporation, September 1997
-- based on SEU Hardening of Field Programmable Gate Arrays (FPGAs) for Space Applications and Device Characterization, R. Katz, R. Barto, et. al., IEEE Transactions on Nuclear Science, Dec. 1994.
Static Hazard
We have covered static hazards. There are also dynamic hazards. An example of a dynamic hazard would be when a circuit is supposed to switch as follows:
0 1
But instead switches:
0 1 0 1
Any circuit that is static hazard free is also dynamic hazard free.
Output Stage
+ i Programmable Load -
Programmable Load
-
IOUT(A)
0.030
0.010
0.000 0 1 2 3 4 5
VOUT
0.080
IOUT(A)
0.060
0.040
0.020
0.000 0 1 2
Vcc-VOUT
IOUT(A)
0.040 0.030 0.020 0.010 0.000 0 1 2 3 S/N LAN4403 S/N LAN4404 S/N LAN4405 S/N LAN4406
VOUT
0.060
IOUT(A)
0.040
0.020
0.000 0 1
Vcc-VOUT
5V CMOS Voltages
VOH - ~VDD (no DC load) VOL - ~GND (No DC load) VIH - 70% VDD VIL - 30% VDD '1' Noise margin = ~30% VDD '0' Noise margin =~30% VDD