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MOS TRANSISTOR

THEORY
UNIT -1
Chapter -2
(Neil weste p:- 41- 91)
Introduction

A MOS transistor is a majority-carrier device,


in which the current in a conducting channel
between the source and the drain is
modulated by a voltage applied to the gate.

NMOS (n-type MOS transistor)


1) Majority carrier = electrons
2) A positive voltage applied on the gate with respect to
the substrate enhances the number of electrons in the
channel and hence increases the conductivity of the
channel.
3) If gate voltage is less than a threshold voltage Vt , the
channel is cut-off (very low current between source &
drain).

PMOS (p-type MOS transistor)


1) Majority carrier = holes
2) Applied voltage is negative
with respect to substrate.
Relationship between Vgs and
Ids, for a fixed Vds:
n-channel enhancement
n-channel depletion
p-channel enhancement
n-channel depletion
Ids
Ids
Ids
Ids
Vgs
Vgs
Vgs
Vgs
+ Vt
+ Vt
- Vt
- Vt

Devices that are normally cut-off with zero


gate bias are classified as
"enhancementmode"devices.

Devices that conduct with zero gate bias are


called "depletion-mode"devices.

Enhancement-mode devices are more


popular in practical use.
nMOS Enhancement
Transistor

At Vds=+V, Vgs=0V, no current flows


from source to drain because they are
insulated by two reverse biased pn
junction
1. Accumulation mode (Vgs << Vt)
2. Depletion mode (Vgs Vt)
3. Inversion mode (Vgs > Vt)

The factors that influence the level of drain current


Ids (b/w S and D)

Distance b/w S and D

Channel width

Threshold voltage Vt

Thickness of SiO2

Dielectric constant of insulator

Carrier mobility
Threshold voltage (Vt):

The voltage at which an MOS device begins to


conduct ("turn on"). The threshold voltage is a
function of
(1) Gate conductor material
(2) Gate insulator material
(3) Gate insulator thickness
(4) Impurity at the silicon-insulator interface
(5) Voltage between the source and the substrate Vsb
(6) Temperature
Threshold voltage (Vt) Equations
Threshold voltage (Vt)equation

Vt ,can be expressed as

Where Vt-mos is the ideal threshold


voltage of an ideal transistor and Vfb is
termed as flat-band voltage.
Body Effect

Effect due to series connection of


transistors

Increases if source voltage increases


because source is connected to the
channel

Increase in Vt with Vs is called the body


effect
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V

<

_
<
'
,

>

MOS device design equations

The cutoff region is also referred to as the


subthreshold region.

The value of Ids is very small


Sub threshold region
Mobility variation

Mobility decreases with increasing


doping concentration and increasing
temperature.
Average carrier drift velocity
(V)
Electric field (E)
=
Thinox
Substrate
SiO2
Poly Si
n n
Source
Gate
Drain

When the gate oxide is very thin, a


current can flow from gate to source or
drain by electron tunneling through the
gate oxide.
Electron Tunneling
Drain punch through

The drain is at a high enough voltage with


respect to the source. Causes current to
flow irrespective of the gate voltage.
Thinox
Substrate
SiO2
Poly Si
n n
Source
Gate
Drain
Hot elections
Due to excess Vds, hot electrons impact the drain,
dislodging holes that are then swept toward the
negatively charged substrate and appear as a
substrate current. This effect is known as impact
ionization
Thinox
p Substrate
SiO2
Poly Si
n n
Source
Gate
Drain
Cgb
C
g
d
C
g
s
Cdb
Small signal AC Characteristics

Output conductance (gds) in the


linear region can be obtained by
differentiating linear equation.

The transconductance expresses the


relationship between output current
ids and input voltage Vgs
1
Vin
Vout 0
CMOS invertors DC characteristics
VDD
GND
Vgsn4
Vgsn3
Vgsn2
Vgsn1
-Vgsp4
-Vgsp2
-Vgsp1
-Vgsp3
Idsn
Idsp
Idsp
Superimposing the two characteristics
A
D
C
E
Vout
VDD
VDD
Vin
A. n/p=10
A
C
B
B. n/p=1
C. n/p=0.1
Vin
Vout
n/p
Ratio

NML = VILmax-VOLmax

NMH = VOHmax-VLIHmin
Noise
Margin
Input /output transfer
curve
A
D
C
E
Vout
VDD
VDD
B
Vin
Vtn
VDD-
Vtp
.
5VD
D
.
5VD
D
A. n/p=10
A
C
B
B. n/p=1
C. n/p=0.1
Vin
Vout
n/p
Ratio

The ratio n/p is decreases the transition region


shifts from left to right
Noise
Margin

Noise Margin:Determines the allowable noise


voltage on the input of a gate so that the output
will not be affect.

Noise Margin is in terms of two parameters LOW


noise margin NML and HIGH noise margin NMH

NML is define as the difference in


magnitude between the maximum LOW
output voltage of the driving gate and the
maximum input LOW voltage recognized by
the driven gate.

NML = VILmax-VOLmax

NMH is define as the difference in magnitude


between the minimum HIGH output voltage of
the driving gate and the minimum input HIGH
voltage recognized by the receiving gate.

NMH = VOHmax-VLIHmin


Static load MOS
inverters

Apart from the CMOS inverter , there are


many other forms of MOS inverter that
may be used to build logic gates

Ex: resistive load inverter

If resister value increases transfer curve


leads to left side.
The Pseudo-nMOS
inverter

Pseudo inverter that uses a p-device pull-


up or load that has its gate permanently
grounded.

An n-device pull-down or driver is driven


with the input signal.

n/p affects transfer characteristic

If nMOS on then Vout=


Saturated load
inverter

An inverter design using nMOS transistor


load.

But remember that the threshold is modified


by the body effect because the source of
the n-load transistor above Vss
Thinox
Substrate
SiO2
Poly Si
n n
Source
Gate
Drain
Thn Q

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