ECE Department Faculty of Engineering University of Santo Tomas

Consists of a combinational circuit to which memory elements are connected to form a feedback path. Receives binary information from external inputs together with the present state of the memory elements to determine the binary value at the output terminals.

Inputs

Combinational Circuit
Memory elements

Outputs

A device with two stable states It can maintain a binary state indefinitely until directed by an input signal to switch states It remains in one of these states until triggered into the other

1.
2. 3.

4.

RS Flip-flop JK Flip-flop D Flip-flop T Flip-flop

NOR Latch

R
S

Schematic symbol Logic Diagram

Transition Table of NOR Latch

Inputs S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Previous State Q(t) 0 1 0 1 0 1 0 1 Present State Q(t+1) 0 1 0 0 1 1 ind ind

NOR Latch

Timing Diagram

NAND Latch

Transition Table of NAND Latch

Inputs S 0 0 0 0 1 R 0 0 1 1 0 Previous State Q(t) 0 1 0 1 0 Present State Q(t+1) ind ind 0 0 1

1
1 1

0
1 1

1
0 1

1
0 1

NAND Latch

Timing Diagram

Schematic symbol

Logic Diagram

Transition Table
Input D Previous State Q(t) Present State Q(t+1)

0
0 1

0
1 0

0
0 1

Schematic symbol

Logic Diagram

Transition Table
Inputs J 0 0 0 0 1 K 0 0 1 1 0 Previous State Q(t) 0 1 0 1 0 Present State Q(t+1) 0 1 0 0 1

1
1 1

0
1 1

1
0 1

1
1 0

Timing Diagram

Schematic symbol

Logic Diagram

Transition Table
Input T Previous State Q(t) Present State Q(t+1)

0
0 1

0
1 0

0
1 1

1.

Level Clocking output of the flip-flop responds during the high (or low) level of the clock signal
a. Positive Level Clocking b. Negative Level Clocking

2.

Edge Triggering the flip-flop produces output only on the rising (or falling) edge of the clock signal
a. Positive Edge Triggering b. Negative Edge Triggering

Positive Level

Negative Level

Positive Edge

Negative Edge

 Two external inputs that initiates the condition or state of the flip-flop

ACTIVE HIGH PR & CLR

ACTIVE LOW PR & CLR

Propagation Delay Time (tP )

This represents the amount of time it takes for the

output of a gate or flip-flop to change states

Setup Time (tSETUP )

It is the minimum length of time the data bit must be

present before the CLK egde hits

Hold Time (tHOLD )

It is the minimum length of time the data bit must be

present after the CLK edge has struck

1.

The waveform below drive a positive edgetriggered RS flip-flop. If Q is low before time A,
a. At what point does Q becomes a 1?

b. When does Q reset to 0?

2.

The clock of the figure below has a frequency of 1 MHz and the flip-flop has a propagation delay time of 25 ns.
a. b. c.

What is the period of the clock? The frequency of the Q output? Its period? How long after the negative clock edge does the Q output change