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CPU Core
10Gb Ethernet
USB model Proprietary model
USB
Control Logic
Proprietary
Bus Controller
PCI Controller
PCI Model
5 December 2003
David W. Smith
AMBA FPU
AMBA FPU
AMBA FPU
SOC 1
DUT
SOC 2
SOC 3
Testbench Requirements
Stimulus Generation
Directed, Random, ATPG, ...
Checkers
Data Protocols
Abstract Modeling
High-level data structures Dynamic Memory
> >
Re-entrant Processes
Re-usability
5 December 2003
David W. Smith
Basic Types
Strings
arbitrary and dynamic length methods to manipulate and convert strings operators for comparison, concatenation and replication
Associative arrays
Indexed by integer, string, or class first(index), last(index), next(index), prev(index), delete(index), and exist(index) methods
Dynamic arrays
integer mem[*]; mem.size();
Linked Lists
doubly linked list of any data type iterator, modification, access methods
5 December 2003
David W. Smith
Input Space
Design
Valid
5 December 2003
David W. Smith
5 December 2003
David W. Smith
Basic Additions
Wild card operators (=?= and !?=) Pass by reference Declaration: task tk( var int[1000:1] ar ); Use: tk( my_array ); // no & needed Argument default values and pass by name Declaration: task foo( int j = 5, int k = 8 ); Use: foo(); foo( 6 ); foo( ,9 ); foo( 6, 9 ); foo(.k(9)); Alias for nets
Short nets in a module
Dynamic Memory
Objects, threads, strings, dynamic and associative arrays Automatically Managed
5 December 2003
David W. Smith
Process Control/Synchronization
Verilog thread support from forkjoin with continuation when all threads complete SV threads use forkjoin with continuation control
all any none
all
any priority
none
3.0 process
Enhanced events (value and duration, passed as arguments) Threads are controlled by
$terminate $wait_child $suspend_thread $exit
5 December 2003
David W. Smith
Clocking Domain
A clocking domain defines a synchronous interface for testbench and properties Every clocking domain has only one clock event Sample and drive timing specified with respect to clock A signal may appear in multiple clocking domains
Input - multiple samples Output default bus resolution
5 December 2003
David W. Smith
10
Synchronous Interface
program name ( port_list ); declarations (class, type, function, clocking...) statements endprogram
5 December 2003 David W. Smith 12
Verification Extensions
Aliases Basic Types
Testbench Specific
Random Constraints
Process Control/Synchronization References
Clocking Domains
Program Block
5 December 2003
David W. Smith
13