Wednesday, September 04, 2013

Block Diagram
External interrupts Interrupt Control On-chip ROM for program code
Timer/Counter

On-chip RAM

Timer 1 Timer 0

Counter Inputs

CPU
Serial Port

OSC

Bus Control

4 I/O Ports

P0 P1 P2 P3

TxD RxD

Address/Data
Wednesday, September 04, 2013

Wednesday, September 04, 2013

Pin Description of the 8051

PDIP/Cerdip
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3.3 (T0)P3.4 (T1)P3.5 (WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND
Wednesday, September 04, 2013

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

8051 (8031)

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Vcc P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14) P2.5(A13) P2.4(A12) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8)

Pins of 80511/4
Vccpin 40 Vcc provides supply voltage to the chip. The voltage source is +5V. GNDpin 20ground XTAL1 and XTAL2pins 19,18 These 2 pins provide external clock. Way 1using a quartz crystal oscillator Way 2using a TTL oscillator Example 4-1 shows the relationship between XTAL and the machine cycle.

Wednesday, September 04, 2013

Pins of 80512/4
RSTpin 9reset It is an input pin and is active highnormally low. The high pulse must be high at least 2 machine cycles. It is a power-on reset. Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost. Reset values of some 8051 registers Way 1Power-on reset circuit Way 2Power-on reset with debounce

Wednesday, September 04, 2013

Pins of 80513/4

EApin 31external access There is no on-chip ROM in 8031 and 8032 . The EA pin is connected to GND to indicate the code is stored externally. PSEN ALE are used for external ROM. For 8051, EA pin is connected to Vcc. PSENpin 29program store enable This is an output pin and is connected to the OE pin of the ROM.
Wednesday, September 04, 2013

Pins of 80514/4
ALEpin 30address latch enable It is an output pin and is active high. 8051 port 0 provides both address and data. The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch. I/O port pins The four ports P0, P1, P2, and P3. Each port uses 8 pins. All I/O pins are bi-directional.

Wednesday, September 04, 2013

Figure 4-2 (a). XTAL Connection to 8051

Using a quartz crystal oscillator We can observe the frequency on the XTAL2 pin. C2 XTAL2 30pF C1 XTAL1 30pF GND

Wednesday, September 04, 2013

Figure 4-2 (b). XTAL Connection to an External Clock Source

N C Using a TTL oscillator XTAL2 is unconnected.

EXTERNAL OSCILLATOR SIGNAL

XTAL2

XTAL1

GND

Wednesday, September 04, 2013

Example :
Find the machine cycle for (a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz. Solution:
(a) 11.0592 MHz / 12 = 921.6 kHz; machine cycle = 1 / 921.6 kHz = 1.085 s (b) 16 MHz / 12 = 1.333 MHz; machine cycle = 1 / 1.333 MHz = 0.75 s

Wednesday, September 04, 2013

RESET Value of Some 8051 Registers:

Register PC ACC B PSW SP DPTR RAM are all zero.

Wednesday, September 04, 2013

Reset Value 0000 0000 0000 0000 0007 0000

Figure 4-3 (a). Power-On RESET Circuit

Vcc

+ 10 uF 30 pF 11.0592 MHz 8.2 K 30 pF 18 X2 9 RST 31 EA/VPP X1

19

Wednesday, September 04, 2013

Figure 4-3 (b). Power-On RESET with Debounce

Vcc

31 10 uF 30 pF

EA/VPP X1

X2 RST 9 8.2 K

Wednesday, September 04, 2013

Pins of I/O Port

The 8051 has four I/O ports Port 0 pins 32-39P0P0.0P0.7 Port 1pins 1-8 P1P1.0P1.7 Port 2pins 21-28P2P2.0P2.7 Port 3pins 10-17P3P3.0P3.7 Each port has 8 pins. Named P0.X X=0,1,...,7, P1.X, P2.X, P3.X ExP0.0 is the bit 0LSBof P0 ExP0.7 is the bit 7MSBof P0 These 8 bits form a byte. Each port can be used as input or output (bi-direction).
Wednesday, September 04, 2013

Port 0
Port 0 occupies a total of 8 pins(32-39) It can be used as input/output port. Each pin must be connected externally to 10 K pull-up resistor. This is due to fact the P0 is an open drain. Port 0 as an output port
With external pull-up resistors connected upon reset, Port 0 is configured as an output port.
Wednesday, September 04, 2013

Port 0
Port 0 as an input port
With the resistors connected to the port 0, in order to make it an input, the port must be programmed by writing 1 to all the bits. Initialization
MOV A,#0FFh MOV P0, A Or MOV P0,# 0FFh Or SETB P0.1 To make P0.1 as input port.
Wednesday, September 04, 2013

Dual Role of Port 0

Port 0 is designated as AD0-AD7,allowing it to use it as both Lower order address lines and Data lines. When connecting an 8051/8031 to the external device, Port 0 provides address and data.

Wednesday, September 04, 2013

Port 1
Port 1 occupies a total 8 pins. It can be used as an Input/Output port. This port does not required any external pull-up resistor. Since it has already internal pull-up. Upon reset the Port 1 will be configured as output port. To make it has an input port, It must be programmed as such by writing 1 to all its bits.
MOV A,#0FF H MOV P1,A
Wednesday, September 04, 2013

Port 2
Port 2 occupies a total of 8 pins (pin 21 thru 28). It can be used as an input or output port. It does not required external pull-up since it has already internal pull-up. Upon reset, Port 2 is configured as an output port. To make port 2 has an input port, it must be programmed by writing 1 to all its bits.
MOV A,#0FF H MOV P2,A
Wednesday, September 04, 2013

Dual role of Port 2

In systems based on 89C51,P2 is used as simple I/O. Port 2 is also designated as A8-A15, indicating its dual function. Since 8051 is capable of accessing 64KB external memory.

Wednesday, September 04, 2013

Port 3pins 10-17

Port 3 does not need any pull-up resistors since it already has pull-up resistors internally. Although port 3 is configured as an output port upon reset, this is not the way it is most commonly used. Port 3 has the additional function of providing signals. Serial communications signalRxD, TxD External interrupt/INT0, /INT1 Timer/counterT0, T1 External memory accesses in 8031-based system/WR, /RD
Wednesday, September 04, 2013

Port 3 Alternate Functions

P3 Bit
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
Wednesday, September 04, 2013

Function
RxD TxD INT0 INT1 T0 T1 WR RD

Pin
10 11 12 13 14 15 16 17

 Example: Write a program to get the x value from P1 and send x2 to P2, continuously . Solution: ORG 0 MOV DPTR, #TAB1 MOV A,#0FFH MOV P1,A L01: MOV A,P1 MOVC A,@A+DPTR MOV P2,A SJMP L01 ;---------------------------------------------------ORG 300H TAB1: DB 0,1,4,9,16,25,36,49,64,81 END

Wednesday, September 04, 2013

I/O Port Programming

Port 1pins 1-8

Port 1 is denoted by P1. P1.0 ~ P1.7 We use P1 as examples to show the operations on ports. P1 as an output port (i.e., write CPU data to the external pin) P1 as an input port (i.e., read pin data into CPU bus)

Wednesday, September 04, 2013

A Pin of Port 0
Read latch
TB2

Internal CPU bus Write to latch

P1.X
Clk Q

P0.X pin M1

TB1 Read pin

P1.x
8051 IC

Wednesday, September 04, 2013

Port 0 with Pull-Up Resistors

Vcc
10 K

P0.0 DS5000 P0.1 P0.2 8751 P0.3 P0.4 8951 P0.5 P0.6 P0.7

Port 0

Wednesday, September 04, 2013

A Pin of Port 1
Read latch
TB2

Vcc
Load(L1)

Internal CPU bus Write to latch

P1.X
Clk Q

P1.X pin M1

TB1 Read pin

P0.x
8051 IC

Wednesday, September 04, 2013

Hardware Structure of I/O Pin

Each pin of I/O ports Internal CPU buscommunicate with CPU A D latch store the value of this pin D latch is controlled by Write to latch Write to latch1write data into the D latch

2 Tri-state buffer
TB1: controlled by Read pin
Read pin1really read the data present at the pin

TB2: controlled by Read latch

Read latch1read value from internal latch

A transistor M1 gate
Gate=0: open Gate=1: close
Wednesday, September 04, 2013

Tri-state Buffer
Output Input

Tri-state control (active high)

Low

Highimpedance (open-circuit)

Wednesday, September 04, 2013

Writing 1 to Output Pin P1.X

Read latch
TB2

Vcc
Load(L1) 2. output pin is

1. write a 1 to the pin

Internal CPU bus Write to latch
D Q

Vcc 1 0
M1

P1.X
Clk Q

P1.X pin

output 1

TB1 Read pin

Wednesday, September 04, 2013

8051 IC

Writing 0 to Output Pin P1.X

Read latch
TB2

Vcc
Load(L1) 2. output pin is

1. write a 0 to the pin

Internal CPU bus Write to latch
D Q

ground 0 1
M1

P1.X
Clk Q

P1.X pin

output 0

TB1 Read pin

Wednesday, September 04, 2013

8051 IC

Port 1 as OutputWrite to a Port

Send data to Port 1 MOV A,#55H MOV P1,A ACALL DELAY CPL A SJMP BACK

BACK:

Let P1 toggle. You can write to P1 directly.

Wednesday, September 04, 2013

Reading Input v.s. Port Latch

When reading ports, there are two possibilities Read the status of the input pin. from external pin value MOV A, PX JNB P2.1, TARGET ; jump if P2.1 is not set JB P2.1, TARGET ; jump if P2.1 is set Figures C-11, C-12 Read the internal latch of the output port. ANL P1, A ; P1 P1 AND A ORL P1, A ; P1 P1 OR A INC P1 ; increase P1 Figure C-17 Table C-6 Read-Modify-Write Instruction (or Table 8-5) See Section 8.3
Wednesday, September 04, 2013

Reading High at Input Pin

Read latch 1. write a 1 to the pin MOV P1,#0FFH Internal CPU bus TB2 Load(L1) 1 1

Vcc

2. MOV A,P1 external pin=High

Q
P1.X

P1.X pin

Write to latch

Clk

M1

TB1 Read pin 3. Read pin=1 Read latch=0 Write to latch=1 8051 IC Wednesday, September 04, 2013

Reading Low at Input Pin

Read latch 1. write a 1 to the pin MOV P1,#0FFH Internal CPU bus TB2 Load(L1) 1 0

Vcc

2. MOV A,P1 external pin=Low

Q
P1.X

P1.X pin

Write to latch

Clk

M1

TB1 Read pin 3. Read pin=1 Read latch=0 Write to latch=1 8051 IC Wednesday, September 04, 2013

Port 1 as InputRead from Port

In order to make P1 an input, the port must be programmed by writing 1 to all the bit. MOV MOV MOV MOV SJMP A,#0FFH P1,A A,P1 P2,A BACK ;A=11111111B ;make P1 an input port ;get data from P0 ;send data to P2

BACK:

To be an input port, P0, P1, P2 and P3 have similar methods.

Wednesday, September 04, 2013

Instructions For Reading an Input Port

Following are instructions for reading external pins of ports:

Mnemonics MOV A,PX JNB PX.Y,.. JB PX.Y,.. MOV C,PX.Y

Examples MOV A,P2 JNB P2.1,TARGET JB P1.3,TARGET MOV C,P2.4

Description Bring into A the data at P2 pins Jump if pin P2.1 is low Jump if pin P1.3 is high Copy status of pin P2.4 to CY

Wednesday, September 04, 2013

Programs on Parallel Bit

WAP to receive the Data from Port 0 and send the Data to Port 1,Port 2, Port 3. WAP to toggle the content of Port 0 continuously using a. Using AAH and 55 H. b. Using the CPL instruction. WAP to receive the data from Port 0 and save the data in bank register R6, R7, R5. WAP to toggle the P1.2 and P1.5 continuously without disturbing other bits. WAP to monitor the P1.5 bit .When it is high, make a low-to-high-to-low pulse on P1.3. WAP to monitor the P2.0. When it is high send 99H to Port1.
Wednesday, September 04, 2013