Logic and Computer Design Fundamentals

Chapter 10 Instruction Set Architecture

Baek Jae Hyun

Overview
Computer Architecture Concepts Operand Addressing Addressing Mode Instruction Set Architectures
RISC & CISC

Instructions
Data-Transfer Instructions Data-Manipulation Instructions Program Control Instructions

Program Interrupt Floating-Point Computations

Computer Architecture Concepts

Machine languages
The binary lang. in which instructions are defined and stored in memory

Assembly language
A symbolic lang. that replaces binary opcodes and addresses with symbolic names and that provides other features helpful to the programmer

Computer Architecture Concepts

Instruction format
Opcode field
Specify the operation to be performed

Address field
Provide either a memory address or an address for selecting a processor register

Mode field
Specify the way the address field is to be interpreted

Computer Architecture Concepts

Basic computer operation cycle
Fetch the instruction from memory into a control register (PC) Decode the instruction Locate the operands used by the instruction Fetch operands from memory (if necessary) Execute the operation in processor registers Store the results in the proper place Go back to step 1 to fetch the next instruction

Computer Architecture Concepts

Register set
All registers in the CPU that are accessible to the programmer
Mentioned in assembly lang. Ex)
Programmer accessible registers Processor status register (PSR) C, N, V, and Z from ALU Stack pointer (SP)

Cf) register file for -program, pipeline registers

Operand Addressing
Fetching operand within instruction
Implied address vs. explicit address

The number of explicitly addressed operands per instruction

Three-address instructions Two-address instructions One-address instructions Zero-address instructions
long instructions

Many steps of executions

Operand Addressing
Arithmetic statement : X=(A+B)(C+D)
Operands are in memory addresses symbolized by the letters A, B, C and D These operands must not be changed by the program

Three-address Instructions
Memory-to-memory architecture
ADD T1, A, B ADD T2, C, D MUL X, T1, T2 M[T1]M[A]+M[B] M[T2]M[C]+M[D] M[X]M[T1]+M[T2]

# of accesses to memory for instructions, addresses, and operands : 21

ADD R1, A, B R1M[A]+M[B] ADD R2, C, D R2M[C]+M[D] MUL X, R1, R2 M[X]R1+R2 # of accesses to memory for instructions, addresses, and operands : 13

Operand Addressing
Three-address Instructions
register-to-register (load/store) architecture
Allow only one memory address
load, store instructions

Ex) X=(A+B)(C+D)
LD LD ADD LD LD ADD MUL ST R1,A R2,B R3,R1,R2 R1,C R2,D R1,R1,R2 R1,R1,R3 X,R1 R1M[A] R2M[B] R3R1+R2 R1M[C] R2M[D] R1R1+R2 R1R1*R3 M[X]R1

# of accesses to memory for instructions, addresses, and operands : 18

Operand Addressing
Two-address Instructions
Ex) X=(A+B)(C+D)
MOVE T1, A ADD T1,B MOVE X,C ADD X,D MUL X,T1 M[T1]M[A] M[T1]M[T1]+M[B] M[X]M[C] M[X]M[X]+M[D] M[X]M[X]+M[T1]

If register-memory architecture
ADD R1,A R1R1+M[A]

Operand Addressing
One-address Instructions
Single-accumulator architecture
A special register called accumulator for obtaining one of the operands and as the location of the result

Ex) X=(A+B)(C+D)
LD ADD ST LD ADD MUL ST A B X C D X X ACCM[A] ACCACC+M[B] M[X]ACC ACCM[C] ACCACC+M[D] ACCACC*M[X] M[X]ACC

Operand Addressing
Zero-address Instructions
Stack architecture
Ex) X=(A+B)(C+D)
PUSH A PUSH B ADD PUSH C PUSH D ADD MUL POP X TOSM[A] TOSM[B] TOSTOS+TOS-1 TOSM[C] TOSM[D] TOSTOS+TOS-1 TOSTOS*TOS-1 M[X]TOS

Stack architecture
Processing expressions
Infix expression Postfix expression is called Reverse Polish notation (RPN)
Ex) (A+B)*C+(D*E) A B + C * D E * +

3 1 2

Stack architecture
Program for evaluating A B + C * D E * +
PUSH A PUSH B ADD PUSH C MUL PUSH D PUSH E MUL ADD
In3 In2 In1 In0 Stack

Addressing Architecture
Memory-to-Memory architecture
All of the access of addressing -> Memory Have only control registers such PC Too many memory accesses

Register-to-Register architecture
Allow only one memory address
load, store instructions

Register-to-Memory architecture
Program lengths and # of memory accesses tend to be intermediate between the above two architectures

Single accumulator architecture

Have no register profile Too many memory accesses

Stack architecture
Data manipulation instructions use no address. Too many memory (stack) accesses Useful for rapid interpretation of high-level lang. programs in which the intermediate code representation uses stack operations.

Addressing Modes

Implied mode Immediate mode Register and register-indirect mode Direct addressing mode Indirect addressing mode Relative addressing mode Indexed addressing mode Base-register mode

Addressing Modes
Implied mode
The operand is specified implicitly in the definition of the opcode.

Immediate mode
The actual operand is specified in the instruction itself.

Addressing Modes
Register mode
Operands are in registers that reside within the processor of the computer Particular register is selected by a register address field in the instruction format

Register-indirect mode
Each of elements in arrays is addressed by register Ex)
ADD (R1)+, 3
M[R1]M[R1]+3, R1R1+1

Addressing Modes
Direct addressing mode

Example Demonstrating Direct Addressing for a Data-Transfer Instruction

Addressing Modes
Direct addressing mode

Example Demonstrating Direct Addressing in a Branch Instruction

Addressing Modes
Indirect addressing mode
Addr. Field of instruction
Address at which the effective address is stored in memory If indirect mode,
ADRS = 500 and M[ADRS] = 800 Effective address : 800

Addressing Modes
Relative addressing mode
Effective addr. = addr. Field of instr. + PC Ex) effective addr. = 252+500

Addressing Modes
Indexed addressing mode
Effective address
= addr. field of instr. + index register (offset)

Base-register mode
Effective address
= base register + addr. field of instr. (offset)

Addressing Modes (Summary)

Base register LDA #ADRS(R1) ACC <- M[R1+ADRS]

Instruction Set Architecture

RISC (Reduced Instruction Set Computer) Architectures
Memory accesses are restricted to load and store instruction, and data manipulation instructions are register to register. Addressing modes are limited in number. Instruction formats are all of the same length. Instructions perform elementary operations

CISC (Complex Instruction Set Computer) Architectures

Memory access is directly available to most types of instruction. Addressing mode are substantial in number. Instruction formats are of different lengths. Instructions perform both elementary and complex operations.

Instruction Set Architecture

RISC (Reduced Instruction Set Computer) Architectures
Large register file Control unit: simple and hardwired pipelining

CISC (Complex Instruction Set Computer) Architectures

Register file: smaller than in a RISC Control unit: often micro-programmed Current trend
CISC operation a sequence of RISC-like operations

Instruction Set Architecture

3 categories of elementary instructions
Data transfer instructions Data manipulation instructions Program control instructions

Data Transfer Instructions

Memory Memory : move, exchange Registers Memory : load, store, exchange Registers Registers : move, exchange

Data Transfer Instructions

Stack instructions
Memory stacks:
A portion of a memory address space. Store state info. related to procedure calls/returns and interrupts

PUSH SP SP 1 M[SP] R1 POP R1 M[SP] SP SP +1

Data Transfer Instructions

I/O instructions
Ports
Registers with I/O lines attached to I/O devices

How to port addresses are assigned

Independent I/O systems
Separate address field for addressing ports

Memory-mapped I/O
No separate memory locations in one common address range No distinct I/O instructions

Data Manipulation Instructions

Arithmetic Instruction Logical and bit manipulation instructions Shift instructions

Arithmetic Instructions

1111 0000 0000 1111

2s complement

Logical and Bit Manipulation Instructions

Mask instruction X0=0 Bit complement X 1 = X

Shift Instructions

Multiple-field format for shift instruction OP REG TYPE RL COUNT

Program Control Instructions

(Examples)
CMP R5, R6, TO1 . . . TO1: CMP R5, R6, R1 TEST R5, R6, R1

Comparison via a subtraction Set or reset status bits

Comparison via a AND Set or reset status bits

Program Control Instructions

CMP R5, R6 BZ TO1 . . . TO1:

Program Control Instructions

CMP R5, R6 BHE TO1 . . . TO1:

Program Control Instructions

CMP R5, R6 BGE TO1 . . . TO1:

Program Control Instructions

Procedure Call and Return Instructions

Main program
int main(void) { puts(Hi, Mom!); }

Subroutine
Code for puts()

Program Control Instructions

main function ... Call function A ...

SP Function A Call

Function A

Main function Stack

Program Control Instructions

CALL B10 . . . ;--------------------------------------B10 PROC CALL C10 RET B10 ENDP ;--------------------------------------C10 PROC RET C10 ENDP ;---------------------------------------

SP SP-1 M[SP] PC PC effective address

PC M[SP] SP SP+1

Program Interrupt
Program interrupt
transfer control from a program that is currently running to another service program as a result of an externally or internally request Handling a variety of situations that require a departure from the normal program sequence

Service program
User program { }

Program Interrupt
External Interrupts
Come from I/O device, timing devices, circuit monitoring power supply, or any other external source
I/O requests, I/O completion Time-out interrupt Power failure interrupt

Internal Interrupts (traps)

Come from illegal or erroneous use of an instruction or data
Arithmetic overflow Divide-by-zero Memory stack overflow Protection violation

Software Interrupts
A special instruction that behaves like an interrupt, used by programmer
System call instruction: Ex) user I/O requests User mode System (OS) mode

Processing Internal Interrupts

Instructions related to EI - ENI: enable interrupt - DSI: disable interrupt

Microinstructions for interrupt

SP SP-1 M[SP] PC ; return addr. SP SP-1 M[SP] PSR EI 0 INTACK 1 PC IVAD ; interrupt vector addr.

Floating-point Computations
Representation: (fraction, exponent)
F 2E = +(0.1001110)2 2+4

Range of numbers
In case of computer with 48-bit registers
Integer: (247-1) Floating-point number: (1-2-35) 2+(2048-1)
Sign: 1bit, Fraction: 35bits, Exponent: 12bits

Floating-point Computations
Arithmetic operations
.5372400 x 102 + .1580000 x 10-1 .5372400 x 102 + .0001580 x 102 .56780 x 105 + .56430 x 105

.5373980 x 102

.00350 x 105
.35000 x 103

.5372400 x 102 x .1580000 x 10-1

Addition

Floating-point Computations
Biased Exponent
Bias: an excess number added to the exponent so that all exponents become positive Advantages
Only positive exponents Simpler to compare the relative magnitude

Floating-point Computations
Standard Operand Format of floating-point numbers
Single-precision data type: 32bits
ADDFS

Double-precision data type: 64bits

ADDFL

IEEE Floating-Point Operand Format

Floating-point Computations
Significand
A leading bit to the left of the implied binary point, together with the fraction in the field

f field 1000 0100 0000

Significand 1.1000 1.0100 1.0000

Decimal Equivalent 1.50 1.25 1.00

s

~
Minimum number 01000..000

~
Maximum number

Floating-point Computations

e=255 (11111111), f=0 +, - e=255 (11111111), f0 NaN (Not-a-Number) , Ex) 0 x = ? e=0 (00000000) , f=0 +0, -0 e=0 (00000000) , f0 < minimum value