Académique Documents
Professionnel Documents
Culture Documents
Embedded Development
C Code
VHDL or Verilog
Code Entry Include the BSP C/C++ Cross Compiler and Compile the Software Image Linker
HDL Entry System Netlist Instantiate the Simulation/Synthesis System Netlist and Implement Implementation the FPGA
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Load Software Into FLASH Debugger
Compiled ELF
Compiled BIT
Embedded Development
Tool Flow Overview
While seemingly complex when viewed in total, the system design flow simply combines the standard hardware flow used to create FPGA bitstreams and standard software flow used to create processor ELF files. In fact, unless on-chip memory resources are used to store the software image, the Embedded Developers Kit can be viewed as nothing more than an extension to the Xilinx core generation tool CoreGen. The first step is to create the System Netlist using the Embedded Developers Kit and instantiate that netlist into the designs HDL code. The hardware design is then synthesized, merged and implemented using the exact same flow as used with any other black box core. While it is common to include a portion of the yet created software image inside the FPGA using block RAM, the Compiled BIT file created during this phase of development only contains the systems hardware description.
Embedded Development
Tool Flow Overview
The second step is to create the Board Support Package (BSP) using the Embedded Developers Kit (EDK) and include the required drivers in the systems C code. The code is then compiled and linked with the various functions available in the BSP as is the same with any other processor system. Because the embedded system is built using the FPGA fabric, the BSP is customized for the particular set of peripherals included in the System Netlist. Unlike an off the shelf general purpose processor, embedded systems in Xilinx FPGA can include any combination of Xilinx provided and user created peripherals. This means that every BSP is potentially unique and as such EDK is tasked with customizing a generic set of drivers as required to properly support the arbitrary processor system. Once the final set of peripherals and bus structures have been solidified, the software and hardware flows can be run independently. Even if part or all of the software image is stored using on-chip block RAM, the software flow does not require running the hardware flow from scratch when making software changes. Only if a change is made to the instantiated System Netlist does the hardware need to be implemented again before a the new software image which relies on the architectural change can be loaded and run.
Embedded Development
Tool Flow Overview
If the software image is completely stored externally, configuring the FPGA and loading the external storage device are performed in exactly the same way as a typical two chip solution. If part or all of the software image is stored using on-chip block RAM and as such is embedded within the FPGAs bitstream, an additional step is required before the FPGA can be configured. EDK provides a tool called Data2MEM which merges the appropriate sections of the Compiled ELF file with the Compiled BIT file. The resulting BIT file is created is typically created in a few seconds and can then be used to configured the FPGA. When the entire software image is stored within the FPGA, only the BIT file is needed to both configure the system and load the software image. If only portion of the software image, such as the bootstrap, is stored within the FPGA, then Data2MEM is run to create a combined BIT file and the system is once again configured/loaded as any two chip solution using the unmerged ELF sections and the combined BIT file.
Embedded Development
Tool Flow Overview
Debugging the software running on the system is performed in the same manner as would be on any general purpose processor. GDB or other debug tool is used to connect to the target and provide runtime control of the target and even load new images when desired. Unlike general purpose processors, the physical system can be probed using ChipScope modules. This capability provides a level of visibility into the operation of the system unmatched by external processors.
EDK tools
Xilinx EDK comprises the following tools:
EDK tools
Base System Builder Wizard
The Base System Builder (BSB) wizard allows you to quickly create a working embedded design, using any features of a supported development board or using basic functionality common to most embedded systems. After you create a basic system, you can then customize it using the tools in XPS and ISE. Xilinx recommends using the BSB.
EDK tools
Software Development Kit
The Xilinx Software Development Kit (SDK) is the recommended development environment for software application projects. SDK is based on the Eclipse open source standard. Note XPS can also be used for software development. However, all software development tools available in XPS is deprecated and will be removed in the 12.1 release.
EDK tools
Bitstream Initializer
The Bitstream Initializer (Bitinit) updates an FPGA configuration bitstream to initialize the on-chip instruction memory with the software executable.
EDK tools
System ACE File Generation
The System ACE file generation tool (GenACE) generates a Xilinx System ACE configuration file based on the FPGA configuration bitstream and software executable to be stored in a non-volatile device in a production system.
A MicroBlaze system can range from a processor core with a minimum of local memory to a large system with many MicroBlaze processors, sizable external memory, and numerous OPB peripherals. MicroBlaze applications can range from software-based simple state machines to complex controllers for Internet appliances or other embedded applications.
On-chip block RAM Standard bus interconnects On-chip Peripheral Bus (OPB) peripherals.
In addition, you can define and add peripherals for custom functions, or as an interface to a design residing in the FPGA.
MicroBlaze Architecture
MicroBlaze Architecture
The MicroBlaze embedded soft core includes the following features:
Thirty-two 32-bit general purpose registers 32-bit instruction word with three operands and two addressing modes Separate 32-bit instruction and data buses that conform to IBMs OPB (On-chip Peripheral Bus) specification Separate 32-bit instruction and data buses with direct connection to on-chip block RAM through a LMB (Local Memory Bus) 32-bit address bus Single issue pipeline Hardware multiplier (in Virtex-II and subsequent devices)
Pipeline Architecture
The MicroBlaze pipeline is a parallel pipeline, divided into three stages:
Fetch Decode Execute
In general, each stage takes one clock cycle to complete. Consequently, it takes three clockcycles (ignoring any delays or stalls) for the instruction to complete.
Load/Store Architecture
MicroBlaze can access memory in the following three data sizes:
Byte (8 bits) Halfword (16 bits) Word (32 bits)
Memory accesses are always data-size aligned. For halfword accesses, the least significant address bit is forced to 0. Similarly, for word accesses, the two least significant address bits are forced to 0. MicroBlaze is a Big-Endian processor and uses the Big-Endian address and labeling conventions shown in Figure 2 when accessing memory. The following abbreviations are used:
MSByte: Most Significant Byte LSByte: Least Significant Byte MSBit: Most Significant Bit LSBit: Least Significant Bit
Ejemplos
Ejemplos. Configuracin 1
Ejemplos.
Ejemplos: Configuracin 3
Ejemplos
Ejemplos: Configuracin 5
Este archivo se crea automticamente mediante las herramientas del EDK, pero es bueno conocer su sintaxis. Referenciar el manual de MicroBlaze.
MicroBlaze Processor
Scalable 32-bit Core
Single-Issue pipeline
Supports either 3-stage (resource focused) or 5-stage pipeline (performance focused)
Hardware Divider Fast Simplex Link FIFO Channels for Easy, Direct Access to Fabric and Hardware Acceleration Hardware Debug and Trace Module
Busses 101
The MicroBlaze processor core is organized as a Harvard architecture
Multi-Port Memory Controller IIC UART
CacheLinks
DXCL Local Memory DLMB ILMB FSL IXCL DPLB MicroBlaze IPLB
LMB Buses
Co-Processor
PLB ARB
MicroBlaze System
Local Memory Bus
BRAM
MicroBlaze
32-Bit RISC Core
Arbiter
0,1.15
Custom Functions Custom Functions
Bus Bridge
CacheLink
10/100 E-Net
Memory Controller
UART
GPIO
On-Chip Peripheral
SDRAM
Arbiter
PLB
OPB