8051 Microcontroller

Designing with Microcontrollers

Tuesday, September 17, 2013

8051 BLOCK DIAGRAM Port 0

I/O A0-A7 D0-D7

ALU

PSW

SFR

Port 1

I/O

Port 2

I/O A8-A15

PC

Port 3

DPTR DPH DPL

ROM

I/O INT CNTR SERIAL RD/WR

Tuesday, September 17, 2013

~EA ALE

System Timing System Interrupt Timers Data Buffers Memory Controls

PSEN
XTAL1 XTAL2 RESET VCC GND

BYTE / BIT ADDRESSIBLE RB3 RB2 RB1 RB0

SFR IE IP PCON SBUF SCON TCON TMOD TL0 TH0

TL1
TH1

INTERNAL RAM STRUCTURE

Tuesday, September 17, 2013

A* E0

B* F0

IP* B8

IE* A8

TMOD 89

TCON* 88

MATH REGISTERS

INTERRUPT REGISTERS

TIMER CONTROL REG

THO 8C

TLO 8A

TH1 8D

TL1 8B

TIMER / COUNTER REGISTERS

SCON* 98

SBUF 99

PCON 87

PSW* D0 FLAGS

SERIAL DATA REGISTERS

SP 81
Tuesday, September 17, 2013

DPTR DPH DPL 83 82

PC

PORT 0* LATCH 80

PORT 1* LATCH 90

PORT 2* LATCH A0

PORT 3* LATCH B0

Tuesday, September 17, 2013

PSW

CY

AC

F0

RS1

RS0

OV

CY AC F0 RS1 RS0

Carry Flag used in arithmetic and Boolean operation Auxiliary Carry, used in BCD arithmetic User Flag 0 Register Bank select bit 1 Register Bank select bit 0

OV P

RS1 RS0 0 0 Select Register Bank 0 0 1 Select Register Bank 1 1 0 Select Register Bank 2 1 1 Select Register Bank 3 Overflow Flag used in arithmetic instructions Parity, shows parity of register A; 1 = Odd Parity

Tuesday, September 17, 2013

TIMERS & COUNTERS

THE TIMER CONTROL (TCON)
7 6 5 4 3 2 1 0

TF1
7 6 5 4 3 TF1 TR1 TF0 TR0 IE1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Timer 1 Overflow flag. Set when timer rolls from all 1s to 0. Cleared when processor vectors to execute interrupt service routine located at program address 001Bh. Timer 1 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by program to halt timer. Does not reset timer. Timer 0 Over flow flag. Set when timer rolls from all 1s to 0. Cleared when processor vectors to execute interrupt service routine located at program address 000Bh. Timer 0 run control bit. Set to 1 by program to enable timer to count; cleared to 0 by program to halt timer. Does not reset timer. External interrupt 1 Edge flag. Set to 1 when a high-to-low edge signal is received on port 3 pin 3.3 (INT 1). Cleared when processor vectors to interrupt service routine located at program address 0013h. Not related to timer operations. External interrupt 1 signal type control bit. Set to 1 by program to enable external interrupt 1 to be triggered by a falling edge signal. Set to 0 by program to enable a low-level signal or external interrupt 1 to generate an interrupt. External interrupt 0 Edge flag. Set to 1 when a high-to-low edge signal is received on port 3 pin 3.2 (INT 0). Cleared when processor vectors to interrupt service routine located at program address 0003h. Not related to timer operations.

IT1

IE0

External interrupt 0 signal type control bit. Set to 1 by program to enable external interrupt 0 to be triggered by a falling edge signal. Set to 0 by program to enable a low-level signal or external interrupt Tuesday, September 17, 0 to generate an interrupt. 2013

IT0

THE TIMER MODE CONTROL (TMOD)

7 6 5 4 3 2 1 0

Gate

C/T

M1
Timer 1

M0

Gate

C/T

M1
Timer 0

M0

7/3 6/2 5/1 4/0

Gate C/T M1 M0

OR gate enable bit which controls Run/ Stop of timer Set to 1 by program to make timer act as counter Mode select bit 1 Mode select bit 0 M1 M0 Mode

0
0 1 1

0
1 0 1

0
1 2 3

Tuesday, September 17, 2013