ARM registers

Total 31 registers each 32 bit. At any time, 16 general registers and 1 or 2 status registers are visible in ARM state. General registers are named R0 to R15. R15 is same as Program Counter (PC). Thus PC can be manipulated in many different ways just like any other general register. For example: MOV R15, R1 instruction is an indirect jump instruction.

ARM registers
R14 is same as Link Register (LR). When a sub-routine is called, return address is automatically saved in LR. BL (Branch and Link) instruction is used to call a sub-routine. e.g. BL delay BL instruction copies return address into LR (i.e. R14) and then transfers control to called routine. There is no RETURN instruction. Instead MOV PC,LR can be used to return from a sub-routine.

ARM registers
Benefit of keeping return address in a register instead of on stack: faster performance because register access is faster than memory. Nested sub-routine calls can over-write the contents of LR. If nested calls are used, LR must be saved on stack. The last sub-routine in the call-chain need not save LR. Compiler automatically decides whether or not to save LR on stack

ARM registers
R13 is often used as Stack Pointer (SP). Theoretically, any register among R0-R13 can be used as stack-pointer. By convention, R13 is used. There are no PUSH or POP instructions. Instead, LDR / STR (with appropriate addressing mode) can be used to access stack. Stack can grow upwards or downwards in memory. Most Compilers implement downwards growing stack. I.e. stack-top is initialized to the end of memory.

ARM registers
CPSR (Current Program Status Register) contains condition code flags (like Z, C) and current mode bits. When an exception occurs: contents of CPSR are automatically copied to SPSR (Saved Program Status Register). It is possible to copy LR into PC and copy SPSR into CPSR in a single instruction. Thus ISR need not save CPSR on stack. However, if nested interrupts are used, then CPSR needs to be saved on stack.

ARM registers
A subset of ARM registers is visible in Thumb state: Only R0 to R7 and PC, LR, SP are directly visible in Thumb state. In the Thumb state: R0-R7 are referred to as Lo registers and R8-R15 are referred to as Hi registers. Lo registers can be accessed in the Thumb state. PC, LR and SP can be accessed as well.

 fetch

The 3-Stage ARM Pipeline

the instruction is fetched from memory

decode
decoding of instruction and generation of control signals

execute
Register(s) read from register bank to perform shift & ALU operations and the result written back to register bank

Pipeline

ARM Operating Modes

protected or exception modes which have associated interrupt sources and their own register sets.
User (usr): Normal ARM program execution state Class 1: Exception caused mode change Abort mode (abt): Entered after an illegal memory accesses (mem fault) as a result of fetching instructions or accessing data Undefined (und): Entered when an undefined or illegal instruction is executed

 Class 2: Interrupt caused mode change FIQ (fiq): Processing Fast Interrupts (Supports data transfer) IRQ (irq): Processing Standard interrupts
Class 3: Software Interrupt Supervisor (svc): Protected mode for the operating system, sw interrupts(SWI) System (sys): A privileged user mode for the operating system, entered when dealing with nested interrupts

Mode Change
Exception: Switch to Abort or Undefined mode Interrupts: Switch to FIQ/IRQ mode System Calls: Switch to Supervisor mode

ARMs visible Register

User Level 15 GPRs, PC, CPSR Remaining registers are used for system-level programming & for handling exceptions

 Thumb

What is TDMI?

16-bit extensions to the 32-bit ARM instruction set

Debug
Additional core signals for debug use

Multiplier
32x8 bit multiplier (enhanced beyond 32x2 bit in ARMv3booths algorithm)

EmbeddedICE Logic
logic/registers to control debug facilities
Thumb & ARM are referred to here as states of the processor

Thumb Features
A subset of the 32-bit ARM instructions that can be compressed into 16-bits:
Selection based on the C compilers needs. Processor core executes both 16- and 32-bit instructions segments.

Thumb programs typically are:

~30% smaller than ARM programs. ~30% faster when accessing 16-bit memory.

Thumb reduces 32-bit system to 16-bit cost:

Consumes less power. Requires less external memory.

Summary:

ARM Architecture:
High performance, low power, low cost architecture Suitable for stand-alone as well as RTOS based applications More suitable for C programming than Assembly Language Built-in JTAG based debugging support Wide range of micro-controllers available based on ARM architecture

Some ARM micro-controllers from various manufacturers

LPC2000 family (Philips). STR7xx family (ST) ADuC7xxx (Analog Devices). AT91RMxxx family (Atmel) ML67xxx family (OKI Semiconductor) LH754xx family (SHARP)

LPC 2148