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INSULATED GATE BIPOLAR TRANSISTOR (IGBT)

NAME: SHUBHANKAR N. DESHKAR (13MPE0077)

INTRODUCTION
The Insulated Gate Bipolar Transistor (IGBT) was first demonstrated by

B.Jayant Baliga in 1979, an Indian Electrical Engineer by origin.


Worked at the General Electric Research and Development cell for 15

years in New York, USA.


Has his name among the Eight

Heroes of the semiconductor

revolution in the American Scientific magazine.


IGBT is a semiconductor device and is a

combination of MOSFET and

Transistors at a cellular level.


Acronyms for IGBT: IGR (insulated gate rectifier), Conductivity Modulated

FET (COMFET), Gain-enhanced MOSFET (GEMFET), BiFET (bipolar FET).

Yardsticks for an ideal semiconductor switch


1)

Very low driving losses: High input impedance. 2) Insignificant ON state or Forward conduction losses. 3) Minimal OFF state or Reverse blocking losses. 4) Extremely low switching losses: Ton and Toff to approach zero.

Need for IGBT:


) A modular Darlington pair gives high current gain but a high ) )

ON state voltage drop. GTO, another competing device, but requires high gate drive current. (750A for 4000V, 3000A). MOSFET being unipolar, ON state resistance increases with D-S voltage capability. Switching losses also increase due to inherent reverse diode. With the above considerations, we need a device which will optimize all the above parameters.

CONSTRUCTION
Only major difference in MOSFET and

IGBT is p+ injecting layer. This layer forms a pn junction and injects minority carriers. N-type drain region has two doping levels viz. lightly and highly doped. Doping level and width of this layer sets the forward blocking voltage. This is a PUNCH-THROUGH design: n+ region (buffer layer). Gives lower ON state drop compared to NPT at the cost of lower reverse BD voltage for device. The Gate in insulated from the body by SiO2 to give high input impedance.

The

p-type body region: considerably different from MOSFET to beat the latch up action of parasitic (p-n-p-n) thyristor. Once it latches up, gate control over the IGBT is lost which is undesirable. Sintered Aluminium metallization and deep p+ diffusion shorts Emitter and Base of NPN transistor. This is done to limit the sum of gains of the 2 transistors below unity. Pseudo-Darlington Configuration. PNP being in the final stage of this configuration, is never allowed to saturate. As saturation avoided, reverse recovery charge and time is reduced. This in turn makes the switch off process faster than BJT. Consequently, the switching frequency is also higher.

PRINCIPLE OF OPERATION

With Gate-Emitter voltage less than THRESHOLD VOLTAGE: No inversion layer in P-

type body and hence IGBT is in OFF state.


The forward voltage applied completely drops across reverse biased junction (J2)

along with the flow of some leakage current.


When Gate-Emitter voltage exceeds the THRESHOLD VOLTAGE: Inversion layer is

formed.
This layer shorts the Emitter and the N- (drain drift) region and electron current

starts flowing from Emitter to the drift region.


This in turn causes substantial hole injection from p+ region to the drift region,

some of which combine with electrons coming from the channel.


Rest of the holes cross the drift region and reach the P type body where they are

collected by the source metallization.

N type drain drift region acts as a base for the output PNP

transistor.
The thickness and doping level of this layer will set the current

gain for this transistor.


Current gain intentionally kept low, so that most of the current

flows via the MOSFET and not via the PNP transistor.
This is done, to reduce the voltage drop across the body spreading

resistance.
This, again, in turn is done to eliminate the possibility of the

unwanted latch-up of the parasitic thyristor.


The voltage drop across the IGBT is mainly reduced due to the

strong conductivity modulation offered by the drain drift region.

TYPES OF IGBTs

SPECIFICATIONS FOR IGBT BUK854-800A

V-I CHARACTERISTICS

MATLAB MODEL

For Vg-e = 8V

For Vg-e = 9V

For Vg-e = 10V

Comparison
S.NO. 1 2
3

Vg-e (V) 8 9 10

Ic (A) Ic (A) (datasheet (simulatio ) n) 13 13.41 20 29 19.72 28.6

THANK YOU