AHPL (A HARDWARE PROGRAMMING LANGUAGE)

Introduction
HDL should have two capabilities, Simulation and Synthesis. Once the circuit described in an HDL is synthesized, the schematic of the circuit is generated which is used by the cad user. Synthesis from VHDL doesnt produces optimum schematics. Even all simulation model in VHDL are not synthesizable. The alternative is to use a language that is designed for synthesis and yet posses all the power of VHDL. AHPL is used for this purpose

 VHDL synthesis subset can be described in AHPL at the same level of abstraction. AHPL is a clock mode register transfer level language with the register as a primitive circuit element. For compilation of AHPL codes, a hardware compiler is needed who is capable of generating a wire list specifying the inter connection of available integrated circuits and a functional simulator which interprets the AHPL description and executes the connection and register transfer.

Some HDLs
CDL: Computer Design Language DDL: Digital System Design Language ISP: Instruction Set Processor. AHPL: A Hardware Programming Language. Verilog VHDL The first four were developed at Academic institute and was used mainly by academia.

AHPL SYNTAX
Variables: Variables in AHPL can be upto 20 characters. First character must be alphabetic and the remaining may be alphabetic or numeric. For example: Count, Bus.. Constant: Bit vector are inserted between two backslash separated by a comma (,).
For example: \0, 0, 0, 1, 1\ Its decimal value is equal to 3.

OPERATORS
Function AND OR XOR ALL BITS OR Symbol &, +, @ +/, / Example AB AB A@B A +/ B

ALL BITS AND ENCODE

TRANSFER BRANCH COMPLEMENT ROW CONCATENATE COLUMN CONCATENATE

&/ , / $
! ,

A/B 5$13=/0, 1, 1,0,1/

A B (3) A!B A,B

CONNECTION

Z=B

Relational Operator in AHPL

Sl. No Operation Symbol

1.
2. 3. 4. 5. 6.

Not Equal to
Equal to Greater Than Greater than or Equal to Less Than Less Than or Equal to

NE
EQ GT GE LT LE

Branch Operations in AHPL:

Unconditional Branch (Destination) Multiple Branch (expression)/(Destination) Branching with conditional operation Operator(Operand1, Operand2) / (Dt.) *Dt.= Destination

Selection Operator for Vector and Matrix:

Sl. No RTL Meaning Notation 1. Aj Jth Column of A 2. Am:n AHPL Notations A[j]

3. 4.
5. 6.

Aj Am:n
A,B A!B

Column m to n A[m:n] of A Jth row of A A<m> Row m to n of A A<m:n> Column A, B Catenation Row Catenation A!B

Standard Function in AHPL:

Sl. No 1. 2. 3. 4. 5. 6. Description Addition Increment Decode Decrement Comparison Associate Symbol ADD(X;Y) INC(X) DCD(X) DEC(X) COMPARE(X:Y) ASSOC(X:Y)

Clocked Transfer between Register:

Unconditional transfer of source register F to destination register R is represented by R F It is assumed that the size of source register and destination register is always same. The arrow pointing in the left denotes a register transfer operation in AHPL. Conditional Transfer a. One destination register R and several source register F1, F2, F3 R(F1!F2!F3)*(a, b, c)

Clocked Transfer b/w Register Contd.

b. One source register F and several destination register R1, R2, R3. (R1!R2!R3)*(a, b, c)F c. Several source register F1, F2, F3 and several destination register R1, R2, R3 (R1!R2!R3)*(a, b, c) (F1!F2!F3)*(d, e, f) The asterisk on the right specifies the conditional selection of a vector to be transferred into a target register.

AHPL Programming
A complete AHPL description of a system consists of Combinational Logic Units (CLUnits) and Module similarly as Entity Declaration and Architecture body in VHDL. Each module partitions the design into control and datapath sections. AHPL module consists of a number of register transfer and\or bus connection that take place in individual control steps. Module Declaration: Module description consist a sequence of steps specifying data transfer and or connection. The syntax for module declaration is: AHPL Module: Module_Name For Example: AHPL Module: Counter AHPL Module : FullAdder

Type Declaration
It is used to declare data types including input and outputs. In AHPL types are little different as we had BIT, Integer, Real, etc. in VHDL. 1. MEMORY 2. INPUTS 3. OUTPUTS 4. BUSSES 5. EXINPUTS 6. EXOUTPUTS 7. EXBUSSES 8. CLUINTS.

 MEMORY, BUSSES AND CLUNITS are local symbols. Their scope are limited to the module they are declared. INPUTS and OUTPUTS are semi-local symbols. EXINPUTS and EXBUSSES are global symbols and can be valued externally and are common to all modules. EXINPUTS and EXOUPUTS are external input and external output of the circuit. The syntax for type declaration is TYPE: symbol <n> [m];

Types Contd

 In the above syntax, n and m are integer that indicates the number of rows and columns of the type. If n or m are 1 they can be eliminated. Some examples of type declaration MEMORY: AC1[4]; AC2[4]; Busy. EXINPUTS: DATAREADY. CLUNITS: INC[2]; ADD[5].

Control sequence
The control sequence consist of a list of steps, each steps starting with a number followed by valid operation separated by semicolon. If two or more instruction are separated by a semicolon they will be executed on the same clock cycle.

AHPL-VHDL Mapping
AHPL Description MODULE: ADDER EXINPUTS: A; B; C. EXOUTPUTS: SUM; CARRY. VHDL Description Entity adder is Port(A, B, C: In bit; SUM, CARRY: Out bit);

BODY SEQUENCE <Module Body> <EndSequence> END

End adder; ARCHITECTURE ADDER is begin

Dataflow

OF

<Architecture Body> END Dataflow;

Handling memory array in AHPL

Sometime it is required to select a word from a memory array such as RAM. The write operation can be described by using the conditional transfer notation as explained below: RAM*DCD(AR) MD Here MD is the memory data register and AR is the address register. The content of memory data register is transferred to RAM memory at address AR. Similarly the following notation is used to read data from RAM memory. MD RAM*DCD(AR)