Vous êtes sur la page 1sur 67

# 3.

Flip Flops

Objective
3a. Identify principles of flip-flop operation.

Flip Flops

Introduction to Flip Flops RS Type Flip Flops D Type Flip Flops T Type Flip Flops J-K Type Flip Flops

Digital Flip-Flops

Constructed by connecting various logic gates together Used extensively in registers and counting circuits Their ability to store binary 1s and 0s make them ideal for temporary storage in memory circuits

Digital Flip-Flops

## Level activated inputs (1 or 0):

SYMBOL

DESCRIPTION Presence of NEGATION INDICATOR on input. Logic low ("0") level is required to satisfy this input.

Absence of NEGATION INDICATOR on input. Logic high ("1") level is required to satisfy this input.

Digital Flip-Flops
DYNAMIC INDICATOR (>). Further defines input requirement. Activating signal will be effective only during a transition from one level to another. Dynamic indicator is always read in conjunction with the absence or presence of a negation indicat or. WITH NEGATION INDICATOR. Input requires a transition from the logic high ("1") level to the logic low ("0") level (negative edge or down clock) to be effective. Any constant (static) logic low ("0") level that might remain after the transition has no effect on the logic function. Negative Edge Or Down Clock >

"1"

"0" > WITHOUT NEGATION INDICATOR. Input requires a transition from the logic low ("0") level to the logic high ("1") level (positive edge or up clock) to be effective. Any constant (static) logic high ("1") level that might remain after the transition has no effect on the logic function. Positive Edge Or Up Clock

"1"

"0"

Digital Flip-Flops

While logic gates operate strictly on logic levels, most flip-flops use the leading or trailing edge of a rectangular waveform on at least one input to cause, or trigger a change in the device

LOGIC "0"

## DOWN-CLOCK/ Trailing Edge Rectangular Waveform

Digital Flip-Flops
TRIGGERS
HIGH LOW

LEVEL

EDGE

TRAILING

Digital Flip-Flops

Digital Flip-Flops

A flip-flop has two states: Set and Reset The Q output determines the state of the flip-flop When Q = 1 (or High), the flip-flop is SET and storing a binary 1 When Q = 0 (or Low), the flip-flop is RESET and storing a binary 0

Digital Flip-Flops
SET
Q 1

1
Q 0

## Basic Flip-Flop Logic Symbol

Digital Flip-Flops
RESET
Q 0

0
Q 1

## Basic Flip-Flop Logic Symbol

When no clock is present this Flip/flop is said to be ASYNCHRONOUS-not controlled by a specific timing pulse.

R-S Flip-Flops

Sometimes referred to as R-S latches Normally level activated and have just two inputs

_ R _ Q
R Q

R-S Flip-Flops
_
S Q S R 1 0 0 1 Q 1 0 Q 0 1 0 0 No Change

_
R Q

1 1 Not Allowed

## R-S Flip-Flop (Logic "1" Activated)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

S R Q

Not Allowed

R-S Flip-Flops
_
S Q S R 0 1 1 0 Q 1 0 Q 0 1 1 1 No Change

_
R Q

0 0 Not Allowed

## R-S Flip-Flop (Logic "0" Activated)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

S R Q

Not Allowed

When a specific timing pulse is applied (clock) this F/F is said to be SYNCHRONOUS

## Clocked RS Flip Flop

Must satisfy clock first. After clock is satisfied acts just like a normal RS.

D-Type Flip-Flops

## Q follows D when clocked If negation on D, Qnot will follow D

D Q D 1 0 1 0 T0 T1 T2 T3 T4 0 0 1 1 T5 C 1 1 Q 1 0

_
Q 0 1

>C

_
Q

0 No Change 0 No Change T6 T7 T8 T9

D C Q

D-Type Flip-Flops
_
D Q D 1 0 1 0 T0 T1 T2 T3 T4 1 1 0 0 T5 C 0 0 Q 1 0 Q 0 1

>C

_
Q

1 No Change 1 No Change T6 T7 T8 T9

D C Q

T-Type Flip-Flops

All T-Type flip-flops are edge triggered Used extensively throughout digital equipment in counting circuits and to divide frequency
_
Q Q T T 0 1 1 0 Q Q Changes States No Changes

>T

_
Q

_
Q

T-Type Flip-Flop
T0 T1 100us T2 T3 T4 T5 T6 T7 T8 T9

T Q

50us

100s

200s

T-Type Flip-Flops

Absence or presence of the negation indicator, (bubble), determines on which edge of the clock the flip-flop will trigger, or toggle
_
Q Q T T 0 1 1 0 Q Q

>T

_
Q

_
Q

## T-Type Flip-Flop (with negation indicator)

T0 T1 100us T2 T3 T4 T5 T6 T7 T8 T9

T Q

50us

J-K Flip-Flops

Workhorse of all flip-flops and most versatile because it can be configured to operate as a R-S, D-type, or T-type flip-flop. Used in counter circuits, frequency dividers and registers The S and R inputs have precedence over all other inputs S J Q
>C K R

_
Q

J-K Flip-Flops
_
Combination# S R J K 0 1 X X 1 0 X X 1 1 X X 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 X X 0 0 X X 0 1 C X X X 1 1 1 1 Q 0 1 1 0 Q 1 0 0 1

J >C K

_
R Q

1 2 3 4 5 6 7 8 9

Not Allowed

## J-K Flip-Flop without Negation Symbols

J-K Flip-Flop
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

S R
J >C K R S Q

J K C

_
Q

## J-K Flip-Flop (Without Negation Symbols) Waveform

J-K Flip-Flop
_
Combination# S R J K 0 1 X X 1 0 X X 0 0 X X 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 X X 1 1 X X 0 1 C X X X 0 0 0 0 Q 1 0 1 0 Q 0 1 0 1 S

J >C K

_
R Q

1 2 3 4 5 6 7 8 9

Not Allowed

## J-K Flip-Flop with Negation Symbols

J-K Flip-Flop
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

S R
J >C K R S Q

J K C

_
Q

## Digital Flip-Flop Summary

S Q

_
R Q

If S=1, R=0a. Set then the b. Reset FF will: c. No Change d. Not Allowed

>C

_
Q

Q T

_
Q

J >C K R S Q

_
Q

a. b. c. d.

## Set Reset Toggle No Change

Digital Flip-Flops
SYMBOL DESCRIPTION TOGGLE input. Each time the input signal transitions to the required input level the flip-flop changes states one time. Any constant activating level that might remain has no effect on circuit operation. Likewise, the return of the input signal to the non-activating level has no effect on circuit operation. (see NOTE 1) SET (PRESET) input. When only the "S" input requirement is satisfied, the flip-flop will assume the "1-state". Return of this input to the non-activating level has no effect on circuit operation. (see NOTE 1) RESET (CLEAR) input. When only the "R" input requirement is satisfied, the flip-flop will assume the "0-state". Return of this input to the non-activating level has no effect on circuit operation. (see NOTE 1) The state of the flip-flop is undefined when both "R" and "S" inputs, including the effect of dependency notation if present, are both satisfied concurrently. The effect may be indicated by means of dependency notation when necessary. T

R-S

Digital Flip-Flops
SYMBOL DESCRIPTION "J" (SET) input. the "J" input has the same effect on the flip-flop as the "S" input, but modified such that both the "J" and "K" input requirements are satisfied simultaneously, the flip-flop will change states (toggle). (see NOTE 1) "K" (RESET) input. the "K" input has the same effect on the flip-flop as the "R" input, but modified such that both the "J" and "K" input requirements are satisfied simultaneously, the flip-flop will change states (toggle). (see NOTE 1) "D" (DATA) input. A "D" input should always be shown further dependent upon another input, generally a "CK" input. When the associated "CK" input requirement is satisfied and the "D" input level requirement (absence or presence of negation indicator) is satisfied, the flip-flop will assume the "1-state". When the "CK" input requirement is satisfied and the "D" input level requirement is not satisfied, the flip-flop will assume the "0-state". When the "CK" input returns to its non activating condition, the flip-flop will remain in the stae ("1" or "0") which exists at that moment in time.

The "C" (CLOCK PULSE) input requirements must be satisfied before any signal applied to the controlled input can have any effect on the circuit. NOTE 1: The logic levels necessary to satisfy input requirements and logic levels produced at the output(s) when the function is activated is defined by the presence or absence of negation indicators

HANDOUT PRACTICE

## R-S PRACTICE PROBLEM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 S S Q R

_
R Q Q

## D-TYPE PRACTICE PROBLEM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 D D C Q C

_
Q Q

## T-TYPE PRACTICE PROBLEM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T Q T Q

_
Q

## J-K PRACTICE PROBLEM

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 S J >C K R S Q R J K C Q

_
Q