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Multi-scale Systems Design and Manufacturing

Characteristics of Common Microfabrication Processes

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Content
General ideas about MEMS and m-FAB

Fundamental issues

Case Studies

Microengine, accelerometeretc

Micro-Fabrication

CVD/PVD Oxidation/Deposition Etching Lithography


http://mems.sandia.gov/scripts/images.asp

Shih-Chi Chen Nov 6, 2006


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In the micro-scale

Machine
Form
Geometry

Function
What?

Flows
Mass

Fysics
Application

Fabrication
Processes

Motion
Interfaces Constraints

Who?
Why? Where?

Momentum
Energy Information

Modeling
Limiting Dominant

Performance
Rate Cost

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Design & manufacture of machines


Function
1

Form

Flows Physics
2

Market research

Conceptual design

Design for manufacture


Fabrication processes
Injection molding Photolithography DRIE

Output f ( Input)
5

Consumer
6 Factory and mfg. systems

Assembly processes
Welding Bolting Riveting Soldering Others

Forging Mill Lathe

Items in dotted lines adapted From 2.008 (Prof. JH Chun)

Grinding
Waterjet, Others
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Fundamental Issues
Fundamental reasons fabrication must be different at microscale

Material properties, size vs. tool, tools


Grain boundary

Lithographic vs. Non-lithographic/ Macro vs. Micro

Quality: resolution: optical vs. mechanical


Rayleighs criterion: Resolution~1.2* / NA

Rate & cost: batch vs. individual

Flexibility: 2D based vs. 3D (need assembly/ material..etc)

Metrology

You cant make it if you cant measure it.


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MEMS overview
MICRO-ELECTRO-MECHANICAL-SYSTEM

MICRO- 10-6 m scale ELECTRO- Electrical circuits/device MECHANICAL- Mechanical structures/device Parasite on matured IC fabrication processes

Miniaturization Engineering

Different Manufacturing Methods


Material

By the end of this lecture, you will be able to


Design basic m-FAB processes Select proper materials

What you need to know?


MEMS Analysis
Course 2 material
Electronics Micro-Fab

Thermal Science

Chemistry

Micro-fluidic Solid Mechanics

Optics

Micro-thermal actuator

PDMS Cell Sorter

Micro Mirror
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Size matters: scales, miniaturization


http://www.icknowledge.com/

nm

0.1mm

10mm

1mm

100mm

10 m

atom

DNA virus

hair bacteria dust MEMS

People

nanotechnology

microsystems meso

macrosystems

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Courtesy: Sang-gook Kim, MIT

~1999 42 x 106 transistors

1947 1 transistor

Chronicles about MEMS


1959: Richard Feyman says, There is plenty of room at the
bottom.

1969: Westinghouse creates the Resonant Gate FET.


1970s: Bulk-etched silicon wafers used as pressure sensors.

1982: Kurt Petersen published Silicon as a Structural


material.

1980s: Early experiments in surface- micromachined


polysilicon. Micromachining leverages the microelectronic industry in late 80s.

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Why do we make things small?

Cost Reduced
Batch Fabrication Larger wafer in diameter

Compatibility
Integration with IC/ electronics Capability of Arrays

Speed Increased
Shorter distance between elements

Avoidable Drawbacks

Noise Amplification High Developing Cost Fundamental Limitations

Reduce RC delay

Rigidity Enhanced
Very High Resonant Frequency Mostly Single Crystal Silicon. No Fatigue!

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Moores law (1964)


Number of transistors per chip doubles every 1.5-2 years

Case Study: Accelerometers

Information store on Si = 2^(Time-1962)

6.152J class note


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Market for small-scale devices

http://www.aero.org/publications/helvajian/helvajian-4.html
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Integrated circuits (ICs)


Start Finish

This picture comes from an excellent introductory discussion about IC fabrication at: icknowledge.com 13/ 50

Integrated circuits: Example-Pentium 4TM


Device characteristics

Source: icknowledge.com

# of transistors

42 000 000

Line width:
P4 die size: US dime size

0.18 m=>( 0.13 m)


224 mm2 248 mm2

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Case Study: Thermal ink jet


Superheat ink 250oC Peak pressure 1.4 MPa Refills in 50ms

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Sang-gook Kim, MIT

Case Study: Accelerometers

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Sang-gook Kim, MIT

Case Study: Pressure sensors

www.evgroup.com

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Sang-gook Kim, MIT

Case Study: Digital Micro Mirrors

www.ti.com

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Case Study: MIT Micro-turbine engine


Real Gas Turbine Engine

http://travel.howstuffworks.com/turbine.htm

Great power-to-weight ratio Generates power or thrust


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Case Study: MIT Micro-turbine engine

Mehra, A, etc.,A six-wafer combustion system for a silicon micro gas turbine engine, Microelectromechanical Systems, Journal of , Volume: 9 , Issue: 4 , Dec. 2000 Mehra, A, etc.,Microfabrication of high-temperature silicon devices using wafer bonding and deep reactive ion etching, Microelectromechanical Systems, Journal of , Volume: 8 , Issue: 2 , June 1999

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Micro-manufacturing

Surface/bulk micro-machining Materials: Silicon Oxidation

Thin film deposition


Photolithography Etching Lift-off Wafer Bonding
MIT MTL ICL, MIT Sandia National Lab 21/ 50
PR Dispenser

Wafer Chuck Spin

K. Pister, Berkeley

MIT Microsystems Technology Lab

MIT microfab facility (Building 39) ICL IC Fab TRL MEMS EML mFluidics Class 10 Class 100 Class 1000

Acid hood

Wafer Stepper

Coater
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Clean rooms

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Process matrix

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Typical Materials
Silicon (Si)

Polymers

Photoresist Polyimide PDMS

Doped Si

Poly silicon

Silicon oxide

Silicon nitride

Ceramics

PZT

Glass, quartz Metals

Al, Au, Ag, Ti, Pt,

Polycrystalline Al (C. V. Thompson)


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MEMS Fab Overview


Silicon

How do you make this?

Using only 2D layer addition and removal

With available processes Micron-level size

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MEMS Fab Overview


Material system: Poly/ SiO2/ HF SiO2 / Poly/ XeF2 SiO2/ SCS/ XeF2 Al/ SCS/ SF6 PR/ SiO2/ HF

W. Tang - Darpa

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Micro-Fabrication Overview
For typical processes

2D

Wafers

Needed for previous example

Devices Sacrificial Etch

Deposition
Oxidation or Deposition

Lithography
Add resist Transfer pattern Remove resist Repeat as Necessary

Etch
Wet isotropic or Wet anisotropic or RIE

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Silicon Wafers

Czochrolski method

http://www.msil.ab.psiweb.com/english/msilhist4-e.html

Molten Si bath

Seed pulled at 2-5 cm/hr

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Silicon Crystal Structure

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Silicon Wafers
Structural properties compared to Steel / Aluminum:
Density sut Material Silicon Steel [1020] g/cc 2.33 7.87 Mpa 4000 420 310 E GPa 130 205 69 CTE x 10-6 4.2 12 24

Aluminum [6061 T6] 2.7

Make Si into a conductor or insulator by doping

Boron, phosphorous, arsenic, antimony 10-3 W-cm 102 W-cm

Resistance Conductors

Semi-conductors

Insulators
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Silicon-On-Insulator (SOI) Wafers


Multi-layered Si / Oxide
1.

Start with Si wafer

Si Base Wafer Oxide Si Base Wafer 2nd Si Wafer Si Base Wafer Si Base Wafer SOI

2.
3. 4.

Grow oxide
Bond 2nd Si wafer to oxide Grind top wafer to size

5.

Repeat if necessary

Expensive~ $400 vs. $30 Reduces process time

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Material Addition / Removal


Additive

Subtractive

Casting Molding Oxidation Deposition


Physical

Machining Grinding Etching


Wet Dry

Evaporation Sputtering
Chemical

CVD
Spin-on
www.memspi.com

MEMS
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Oxidation
Forming Silicon Dioxide by oxidation

O2 chamber @ 800-1200 oC (steam optional) Silicon reacts with O2 to grow oxide

2 micron max film thickness

O2 chamber

3hr, 1000 C

O2 chamber Oxide

1m

Si Wafer

Si Wafer

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Oxidation
Forming Silicon Dioxide by oxidation

Uses: insulation, masking, sacrificial layer


Easy to grow and etch (HF) Good insulator/ diffusion barrier (Ex. B, P, As) High dielecytic breakdown field (500 V/mm); = 1016 ohm-cm Good Ge/ GaAs => higher mobility/direct bandgap, but no stable oxide

=> Cant make MOS device

O2 chamber

3hr, 1000 C

O2 chamber Oxide

1m

Si Wafer

Si Wafer
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Chemical Vapor Deposition


Gases react to deposit film on surfaces Example: Polysilicon at 580-650C

Si H 4 Si 2H 2
Typical CVD Furnace:

ICL, MIT
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Evaporation
Metal evaporated w/ electron beam Vacuum environment prevent oxidation, directional vapor travel

Can get shadowing:

S. G. Kim, MIT

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Sputtering
Materials: Metals and dielectrics Requires high vaccuum Argon ions bombard material target

Ejected material - ballistic path to wafers

S. G. Kim, MIT
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Deposition Issues
Thermal compatibility

Topographic compatibility Residual stresses

Deposition over features


Non-conformal

Conformality:

Conformal

Non-conformal

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Photolithography
Photoresist (PR) used to transfer patterns Viscous PR spun onto wafer

Dispense, then spin Speed controls thickness

Thickness: 1 10mm Requires baking (~100C)

7mm Positive Thick Resist 1. Dispense, Spin 3500rpm 2. Pre-bake 90C 60min 3. UV mask expose 15 sec 4. Develop in aqueous solution 5. Post-bake 90C 30min

PR

Dispenser Wafer Chuck Spin Xrpm

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Photolithography
Expose PR to UV light thru mask

Properties change in exposed regions Masks: laser etched or print-transferred chrome

Positive resist destroy bonds, soluble Negative resist crosslinking, less soluble
We use:
PR Substrate

Positive
UV light Expose

Negative
Substrate

Mask

PR Reaction

Develop
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Material Removal - Etching


Bulk micromachining remove Si substrate Surface micromachining add / remove films Masks for etch surface:

Photoresist

oxide, nitride

http://www.ti. com/dlp/reso urces/library

Isotropic vs. anisotropic Wet vs. dry etch

Deep Reactive Ion Etching

K. Pister, Berkeley

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Material Removal - Etching

Williams, et al., J. MEMS Vol 5, no 4 1996

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Wet vs. Dry Etching


Wet etch

Dry etch

Chemical reaction

Reactive ion etching (RIE) High res High cost Very directional Unlimited 2D geometries 0.1 10 microns/min

Low res
Low cost Hard to control direction

Limited 2D geometries
1 10s of microns/min

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Isotropic vs. Anisotropic Etching


Isotropic same etch rate in all directions

Etch depth / surface uniformity problems Diffusion dependent Etch silicon wafer and deposited films

Anisotropic crystal plane dependent


<111>
54.7

Etch ratios more than 100:1 silicon wafers only Crystal planes:

<100> Si

Adapted from: S.M. Sze, Semiconductor Devices

S. G. Kim, MIT
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Deep Reactive Ion Etching


Alternating RIE - polymer deposition

Protection of side walls during material removal

CHF3/Ar forms Teflon-like layer


Issues: Scalloping and tapering

Milanovic et al, IEEE TED, Jan. 2001.


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Reverse Resist and Lift-Off


Process:
PR 1. Apply and pattern reverse resist Need negative sidewalls Positive resist negative image 2. Deposit desired film Evaporation Typically metal 3. Dissolve photoresist, lift-off film Substrate

Limited thickness need non-conformal film

Limited deposition methods PR compatibility


Not typically used in semiconductor industry
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Wafer Bonding
Combine complex shapes from multiple wafers Si-Si wafers

Fusion bonded wafer stack

Low temp (450C) Fusion high temp (1000C) Adhesive epoxy, PR

MIT Microengine Project

Si-Glass wafers

Anodic low temp, high voltage (700V)

M. Schmidt, 2000
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Exercise 1: Design a micro-structure


Reverse engineer the m-FAB processes for the structure shown below.
Thickness=100mm Thickness=1mm

Hint:

Start with SOI wafers

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Exercise 2: Design a Micromotor


Design the m-FAB processes & Select the materials for a micro-motor with cross-section view below

Beerschwingert et al. 1994

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Conclusion
Micro-fabrication is DIFFICULT: Many of them are still vibrant fields of research
Micro-fabrication is EXPENSIVE at developing stage: ~18k/ year @MIT

NEXT: Micro-actuation/sensing/metrology

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