CA Lecture-4

Organization of computer System

The ISA of a computer describes what a computer can

do , but provides no information how to use it.

The ISA describes instructions that a computer can

process but says nothing about how the processor access these instructions.
The system designer needs more information than the

ISA provides in order to design a complete computer system.

Organization
A simple computer has three primary subsystems.

The central processing unit or CPU.

performs many operations and controls the computer. The Memory Subsystem. used to store programs along with data. Input/output or I/O subsystem allows the CPU to interact with input and output devices.

Generic Organization of Computer System

System busses.
Physically a BUS is a set of wires. The components of the computer are connected to the

Busses. To send information from one component to another, the source component outputs data onto the bus. The destination component then inputs this data from the bus. As the complexity of the system grows , it becomes more efficient to at using busses rather than direct connections between every pair of devices.

 The system shown in the generic diagram has three

busses. Address bus. when the CPU read data or instruction from or writes data to memory , it must specify the address of the memory location it wishes to access.
it outputs this address bus; memory inputs this address from the address bus and uses it to access proper memory location.

 Each i/o device , such as such as keyboard , monitor ,

or disk drive , has a unique address as well. When accessing an i/o device, the CPU places the address of the device on the address bus. Each device can read the address off the bus and determine whether it is the device being accessed by the CPU. Address bus receives data from CPU the CPU never reads the address bus.

Data bus.
Data is transferred via the data bus. When CPU fetches data from memory, it first outputs

the memory address on its address bus, then memory

outputs the data onto the data bus; CPU can then read the data from data bus. When writing data to memory, the CPU first outputs the address onto the address bus, then outputs the data on data bus. Memory then reads and stores the data at proper location. The process for reading data from and writing data to i/o devices is similar.

Control bus.
The control bus is different from the other two busses.

Timing diagram for a) memory read b) memory write.

CPU internal organization

Internal linear organization of an 8 x 2 ROM chip

Internal two dimensional organization of an 8 x 2 ROM chip

An 8 x 4 memory subsystem constructed from two 8 x 2 ROM chip.

A 16 x 2 memory subsystem constructed from two 8 x 2 ROM chip with a) high order interleaving.

b) Low order interleaving

An 8x4 memory subsystem constructed from 8x2 ROM chip with controlvsignals.

 Little endian
Big endian