Priority Encoder

ECE 331 Digital System Design
Multiplexers and Demultiplexers, and Encoders and Decoders

(Lecture #15)
The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.
Material to be covered
Supplemental
Chapter 9: Sections 1 4
Fall 2010
ECE 331 - Digital System Design
Multiplexers
Fall 2010
Multiplexers
A multiplexer has
N control inputs
2N data inputs 1 output
A multiplexer routes (or connects) the selected data input to the output.
The value of the control inputs determines the data input that is selected.
ECE 331 - Digital System Design 4
Fall 2010
Multiplexers
Data inputs Control input

Fall 2010
Z = A.I0 + A.I1
Multiplexers
A 0 0 1 1 B 0 1 0 1 F I0 I1 I2 I3
MSB
LSB
Z = A.B'.I0 + A'.B.I1 + A.B'.I2 + A.B.I3

Fall 2010 ECE 331 - Digital System Design 6
Multiplexers
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F I0 I1 I2 I3 I4 I5 I6 I7
MSB
LSB
Z = A.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 + A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3

Fall 2010 ECE 331 - Digital System Design 7
Multiplexers
Fall 2010
8-to-1 Multiplexer in VHDL
Fall 2010
8-to-1 Multiplexer in VHDL
Fall 2010
10
Multiplexers
Exercise:
Design an 8-to-1 multiplexer using 4-to-1 and 2-to-1 multiplexers only.
Fall 2010
11
Multiplexers
Exercise:
Design a 16-to-1 multiplexer using 4-to-1 multiplexers only.
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12
Multiplexer (Bus)
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13
Demultiplexers
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14
Demultiplexers
A demultiplexer has

N control inputs 1 data input 2N outputs
A demultiplexer routes (or connects) the data input to the selected output.
The value of the control inputs determines the output that is selected.
A demultiplexer performs the opposite function of a multiplexer.

Fall 2010
Demultiplexers
Out0
In
Out1 Out2
Out3
S1 S0
W X Y Z
W = A'.B'.I X = A.B'.I Y = A'.B.I Z = A.B.I
A B
A
0 0 1
B
0 1 0
W
I 0 0
X
0 I 0
Y
0 0 I
Z
0 0 0
1
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I
16
Decoders
Fall 2010
17
Decoders
A decoder has

N inputs 2N outputs
N
A decoder selects one of 2 outputs by decoding the binary value on the N inputs.
The decoder generates all of the minterms of the N input variables.
Exactly one output will be active for each combination of the inputs.
What does active mean?
Fall 2010
Decoders
Out0
B A
msb
I0 I1
Out1 Out2 Out3
W X Y Z
W = A'.B' X = A.B' Y = A'.B
Z = A.B
Active-high outputs
A 0 0 1 1
Fall 2010
B 0 1 0 1
W 1 0 0 0
X 0 1 0 0
Y 0 0 1 0
Z 0 0 0 1
19
Decoders
Out0
B A
msb
I0 I1
Out1 Out2 Out3
W X Y Z
W = (A'.B')' X = (A.B')' Y = (A'.B)'
Z = (A.B)'
Active-low outputs
A 0 0 1 1
Fall 2010
B 0 1 0 1
W 0 1 1 1
X 1 0 1 1
Y 1 1 0 1
Z 1 1 1 0
20
Decoders
msb
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21
3-to-8 Decoder in VHDL
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22
3-to-8 Decoder in VHDL
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23
Decoder with Enable

high-level enable
B A Enable
En 1 1 1 1 0 A 0 0 1 1 x
I0
I1 En
Out0 Out1 Out2 Out3
W X Y Z
B 0 1 0 1 x
W 1 0 0 0 0
X 0 1 0 0 0
Y 0 0 1 0 0
Z 0 0 0 1 0
24
enabled
disabled
Fall 2010
Decoder with Enable

low-level enable
B A Enable
En 0 0 0 0 1 A 0 0 1 1 x
I0
I1 En
Out0 Out1 Out2 Out3
W X Y Z
B 0 1 0 1 x
W 1 0 0 0 0
X 0 1 0 0 0
Y 0 0 1 0 0
Z 0 0 0 1 0
25
enabled
disabled
Fall 2010
2-to-4 Decoder with Enable in VHDL
Fall 2010
26
Decoders
Exercise:
Design a 4-to-16 decoder using 2-to-4 decoders only.
Fall 2010
27
Encoders
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28
Encoders
An encoder has

2N inputs N outputs
An encoder outputs the binary value of the selected (or active) input. An encoder performs the inverse operation of a decoder. Issues

What if more than one input is active?
What if no inputs are active?

Fall 2010
Encoders
D C
I0 I1 I2 Out0 Out1
B
A
Z Y
I3
A 0 0 0 1
Fall 2010
B 0 0 1 0
C 0 1 0 0
D 1 0 0 0
Y 0 0 1 1
Z 0 1 0 1
30
Priority Encoders
If more than one input is active, the higher-order input has priority over the lower-order input.
The higher value is encoded on the output
A valid indicator, d, is included to indicate whether or not the output is valid.
Output is invalid when no inputs are active
d=0 Output is valid when at least one input is active

d=1
Why is the valid indicator needed?
Fall 2010
Priority Encoders
msb
Valid bit
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32
VHDL: 4-to-2 Priority Encoder

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY priority IS PORT ( w y z END priority ;
4 input bits
: IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; : OUT STD_LOGIC ) ;

valid indicator 2 output bits
ARCHITECTURE Behavior OF priority IS BEGIN y <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE "01" WHEN w(1) = '1' ELSE "00" ; z <= '0' WHEN w = "0000" ELSE '1' ; END Behavior ;
Active-high inputs and outputs
33
Designing logic circuits using multiplexers
Fall 2010
34
Using an n-input Multiplexer
Use an n-input multiplexer to realize a logic circuit for a function with n minterms.
m = 2n, where m = # of variables in the function
Each minterm of the function can be mapped to an input of the multiplexer. For each row in the truth table, for the function, where the output is 1, set the corresponding input of the multiplexer to 1.
That is, for each minterm in the minterm expansion of the function, set the corresponding input of the multiplexer to 1.
Set the remaining inputs of the multiplexer to 0.
Fall 2010
Using an n-input Mux
Example: Using an 8-to-1 multiplexer, design a logic circuit to realize the following Boolean function F(A,B,C) = Sm(2, 3, 5, 6, 7)
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36
Using an n-input Mux
Example: Using an 8-to-1 multiplexer, design a logic circuit to realize the following Boolean function F(A,B,C) = Sm(1, 2, 4)
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37
Using an (n / 2)-input Multiplexer
Use an (n / 2)-input multiplexer to realize a logic circuit for a function with n minterms.
m = 2n, where m = # of variables in the function
Group the rows of the truth table, for the function, into (n / 2) pairs of rows.
Each pair of rows represents a product term of (m 1) variables.
Each pair of rows can be mapped to a multiplexer input.
Determine the logical function of each pair of rows in terms of the mth variable.
Fall 2010
If the mth variable, for example, is x, then the possible values are x, x', 0, and 1.
38
Using an (n / 2)-input Mux

Example: F(x,y,z) = Sm(1, 2, 6, 7)
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39

Example: F(A,B,C,D) = Sm(1,3,4,11,1215)
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40
The design of a logic circuit using an (n / 2)-input multiplexer can be easily extended to the use of an (n / 4)-input multiplexer.
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41
Designing logic circuits using decoders
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42
Using an n-output Decoder
Use an n-output decoder to realize a logic circuit for a function with n minterms.
Each minterm of the function can be mapped to an output of the decoder.

For each row in the truth table, for the function, where the output is 1, sum (or OR) the corresponding outputs of the decoder.
That is, for each minterm in the minterm expansion of the function, OR the corresponding outputs of the decoder.
Leave remaining outputs of the decoder unconnected.

Fall 2010
Example: Using a 3-to-8 decoder, design a logic circuit to realize the following Boolean function F(A,B,C) = Sm(2, 3, 5, 6, 7)
Fall 2010
44
Example: Using two 2-to-4 decoders, design a logic circuit to realize the following Boolean function F(A,B,C) = Sm(0, 1, 4, 6, 7)
Fall 2010
45

Priority Encoder

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ECE 331 Digital System Design

Multiplexers and Demultiplexers, and Encoders and Decoders

ECE 331 - Digital System Design

ECE 331 - Digital System Design

Data inputs Control input

Z = A.B'.I0 + A'.B.I1 + A.B'.I2 + A.B.I3

Z = A.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 + A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3

ECE 331 - Digital System Design

8-to-1 Multiplexer in VHDL

ECE 331 - Digital System Design

8-to-1 Multiplexer in VHDL

ECE 331 - Digital System Design

Design an 8-to-1 multiplexer using 4-to-1 and 2-to-1 multiplexers only.

ECE 331 - Digital System Design

Design a 16-to-1 multiplexer using 4-to-1 multiplexers only.

ECE 331 - Digital System Design

ECE 331 - Digital System Design

ECE 331 - Digital System Design

N control inputs 1 data input 2N outputs

A demultiplexer performs the opposite function of a multiplexer.

W = A'.B'.I X = A.B'.I Y = A'.B.I Z = A.B.I

ECE 331 - Digital System Design

ECE 331 - Digital System Design

Out1 Out2 Out3

W = A'.B' X = A.B' Y = A'.B

ECE 331 - Digital System Design

Out1 Out2 Out3

W = (A'.B')' X = (A.B')' Y = (A'.B)'

ECE 331 - Digital System Design

ECE 331 - Digital System Design

3-to-8 Decoder in VHDL

ECE 331 - Digital System Design

3-to-8 Decoder in VHDL

ECE 331 - Digital System Design

Decoder with Enable

Out0 Out1 Out2 Out3

ECE 331 - Digital System Design

Decoder with Enable

Out0 Out1 Out2 Out3

ECE 331 - Digital System Design

2-to-4 Decoder with Enable in VHDL

ECE 331 - Digital System Design

Design a 4-to-16 decoder using 2-to-4 decoders only.

ECE 331 - Digital System Design

ECE 331 - Digital System Design

What if more than one input is active?

What if no inputs are active?

ECE 331 - Digital System Design

The higher value is encoded on the output

A valid indicator, d, is included to indicate whether or not the output is valid.

Output is invalid when no inputs are active

d=0 Output is valid when at least one input is active

ECE 331 - Digital System Design

VHDL: 4-to-2 Priority Encoder

: IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; : OUT STD_LOGIC ) ;

Active-high inputs and outputs

Designing logic circuits using multiplexers

ECE 331 - Digital System Design

Using an n-input Multiplexer

m = 2n, where m = # of variables in the function

Set the remaining inputs of the multiplexer to 0.

Using an n-input Mux

ECE 331 - Digital System Design