Steps involved in chip fabrication are

1. All the devices on the wafer are made at the

same time.
2. After the circuitry has been placed on the chip,
the chip is overglassed to protect it. Only those
areas which connect to the outside world will
be left uncovered.
3. The wafer finally passes through a test station.
Test probes send test signal patterns to the chip
and monitor the output of the chip.
4. The yield of a process is the percentage of die
which pass this testing.
5. The wafer is then scribed and separated up into
individual chips. These are then packaged.
6. Chips are ‘binned’ according to their
performance.
1. CMOS Technology
- First proposed in 1960s but was not seriously
considered until the severe limitations in power
density and dissipation occurred in NMOS
circuits.
- Now this is the most dominant technology in IC
manufacturing. It employs both PMOS and
NMOS transistors to form logic elements.
-Advantage : It’s logic elements draw significant
current only during the transition from one state
to another. Hence power is conserved.
 PULL UP
OUTPUT
INPUT

PULL
DOWN
 VDD

INPUT OUTPUT
 VDD

B
2. BiCMOS

A known deficiency of MOS technology is its limited load driving

capabilities. Bipolar transistors have higher gain, better noise

characteristics and better high frequency characteristics. These gates

can be an efficient way of speeding up VLSI circuits. CMOS

fabrication process can be extended for BiCMOS. This transistor

consist of three regions-source, gate and drain. If the source and

drain regions are doped with N-type material and substrate with P-

type then it is called as N-channel MOSFET. If the source and drain

regions are doped with P-type material and substrate with N-type

then it is called as P-channel MOSFET.

 Polysilicon Gate
SiO2
Insulator L D D
W
Source Drain
G SB G
n+ n+
channel

p substrate S S
substrate connected
n transistor to GND
 Polysilicon Gate
SiO2
Insulator L D
W
Source Drain
G SB G
p+ p+
channel

n substrate S substrate connected
to VDD

p transistor
- Wafer Processing
- Photolithography
- Oxide Growth & Removal
- Material Deposition & Removal
- Diffusion of Impurities
- Putting it all together
- Start with crucible of
molten silicon
(≈1425oC)
- Insert crystal seed in
melt Molten
- Slowly rotate / raise Crucible Silicon
seed to form single
crystal boule
- After cooling, slice
boule into wafers &
polish
Current
production:
200mm (10”)
Newest
technology: 300mm
(12”)

Die ­ Single IC chip
300mm wafer
Image Source: Intel Corporation
- All dice on wafer processed simultaneously
- Each mask has one image for each die
- The basic approach:
- Add & selectively remove materials
 Metal - wires
 Polysilicon - gates
 Oxide - insulation
 Selectively diffuse impurities
Photolithography is the key
- Coat wafer with photoresist
(PR)
- Shine UV light through
mask to selectively expose
PR UV Light

- Use acid to dissolve Mask

Photoresist
exposed PR
Wafer
- Now use exposed areas for
- Selective doping
- Selective removal of material
under exposed PR
- Thin Oxide
- Add using chemical deposition
-Used to form gate insulator & block active areas
- Field Oxide (FOX) - formed by oxidation
- Wet (H20 at 900oC - 1000oC) or Dry (O2 at 1200oC)
- Used to insulate non-active areas SiN / SiO2

FOX FOX
SiO2 Thin Oxide

Silicon Wafer Silicon Wafer
- Introduce dopant via
epitaxy or ion implant e.g. Blocking Material 
Arsenic (N), Boron (P) (Oxide)

- Allow dopants to diffuse at

Diffusion
high temperature
- Block diffusion in selective
areas using oxide or PR Silicon

- Diffusion spreads both

vertically, horizontally
- Need to accommodate both N, P transistors
-Must implement in separate regions - wells
(tubs)
 N-well
 P-well

-Alternate approach: Silicon on Insulator (SOI)

n well p well n epi p epi

p substrate n substrate n tub p tub insulator
n­well p­well twin­tub SOI
- Overall chip doped as p substrate, tied to GND
- Selected well areas doped n, tied to VDD

Gnd VDD

n+ n+ p+ p+
channel channel

p substrate n well
- Substrate
- Well
- Active
Areas
- Gates
- Diffusion
- Insulator
- Contacts
- Metal n well
P substrate
wafer
1. Mask Design using Layout Editor
- user specifies layout objects on different layers
- output: layout file
2. Pattern Generator
- Reads layout file
- Generates enlarged master image of each mask layer
- Image printed on glass reticle
3. Step & repeat camera
- Reduces & copies reticle image onto mask
- One copy for each die on wafer
- Note importance of mask alignment
1. The dielectric constant of SiO2 is 3.9. This gives
rise to a large coupling capacitance between
wires which has to be minimized. The solution
is to use low-k dielectrics and the proposed
materials should have approx K=3
2. Another problem arises due to small electric
field under transistor gates which has to be
maximized. The solution is to use high-k
dielectrics and the proposed materials would
have K>>4 .
- Most photolithography is done using UV with
248nm wavelength. But if the wavelength is
less than the value, it gives rise to interference
problems.
- The solution to this are:
1. Optical proximity correction (OPC)
2. Phase-shifting masks
3. Other light sources: 193nmUV, Extreme UV,
X-Rays, E-beam lithography.
- Normal mask - light spreads & overlaps
- Phase shifting mask - cancels overlap
- Drawback: requires 2 masks per litho. step
(Expensive)

Graphic source: Numerical Technologies

Optical switches are generally used as :-
a. HDMI (High Definition Multimedia Interface)
It is an audio video interface that is use to
transmit both digital audio and video streams
of data which are uncompressed and
encrypted. For instance, many consumer
electronics such as high definition flat panel
TVs, DVD disc players, Set Top Boxes, AV
receivers and Camcorders, etc now offer the
option of HDMI connections for a true digital
experience.
b. Nano-optical switches-
restores sight
This helps in developing the
treatments for eye diseases
such as the loss of light
detectors in the retina which
is the major cause of
blindness. So some nano-
photoswitches are put in the
cells of the retina for
‘restoring light sensitivity’ in
people with degenerative
blindness.
 IBM Extends Industry Leading Custom Chip
Technology to Embedded Devices
IBM has announced two new 65 nanometer
Application-Specific Integrated Circuit (ASIC)
product offerings, including the company's first
ever comprehensive low power ASIC offering for
the fast growing wireless, mobile and consumer
electronics market. An ASIC is an integrated
circuit customized for a particular use, rather than
intended for general-purpose use. Usually, a chip
designed solely to run in a cell phone is an
example of an ASIC.
UEGO control circuit board portion with ASIC:-
A method and apparatus for controlling Universal
Exhaust Gas Oxygen (UEGO) sensors comprises an
application specific integrated circuit (ASIC) that
includes a sensor control utilizing proportional-
integral-derivative control loop, sensor drivers for
generating pumping currents that reflect the
changes of voltages representative of oxygen levels
in the reference and test chambers of the UEGO
sensor, a communication circuit for
communicating with an engine control module,
and output buffers for conditioning replications of
the pumping current for delivery to an output
circuit.
A TV graphics demonstration system is a
multimedia application based on PC, intended
for home entertainment. The main functions of
the system are graphics superimposing and
screen capture. The system is implemented and
verified by the PC-added video and graphics
evaluating board.
FPGA, DSP, ASIC growth is driven by demand
for flexibility in Medical Imaging Equipment.
Medical imaging equipment demands various
processing requirements based on the specific
data acquisition principles and algorithms used
in image processing. the advantages of FPGA
in digital signal processing over other
processors and custom IC [integrated circuit]
make it a viable alternative for most
equipment, including current generation
PET [positron emission tomography] machines
and volume imaging conducted in CT [CAT
scan] that requires high performance