Vous êtes sur la page 1sur 16

SIEMENS

BINARY & LOGIC OPERATION

SIEMENS
SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved

1/8

November 21, 2013

SIEMENS

Objectives

- Review On The Logic Gates & How It Is represented In LAD, STL, FBD - Know The Set-Reset Functions.

- Know The Pulse Edge & Mid-Line Coil.


- Know The Jump Condition.

SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved

2/8

November 21, 2013

SIEMENS

OR Gate
S3 (I 0.2)

AND Gate
S1 (I 0.0)

S4 (I 0.3)

Circuit Diagram

S2 (I 0.1)

L3 (Q 8.2)

L1 (Q 8.0) Q 8.2 I 0.0 I 0.1

L2 (Q 8.1)

I 0.2
I 0.3

Q 8.0
Q 8.1

LAD Diagram

I 0.2 I 0.3

>=1

Q 8.2 =

I 0.0

&

FBD Diagram

I 0.1

Q 8.0 = Q 8.1 =

O O =
SIMATIC S7

I 0.2 I 0.3 Q 8.2

STL
3/8

A A = =

I 0.0 I 0.1 Q 8.0 Q 8.1


November 21, 2013

SIEMENS LTD EGYPT 2007 All Rights Reserved

SIEMENS

XNOR Gate
S1 (I 0.6) S2 (I 0.7) S1 (I 0.6) S2 (I 0.7)

XOR Gate

Circuit Diagram

S1 (I 0.4) S2 (I 0.5)

S2 (I 0.5) S1 (I 0.4)

L1 (Q 8.0) I 0.6 I 0.7

L1 (Q 8.0)

Q 8.0

LAD Diagram
I 0.6 I 0.7

I 0.4

I 0.5

Q 8.0

I 0.4

I 0.5

I 0.6 I 0.7 I 0.6 I 0.7


AN AN O A A =

& >=1 &


I 1.0 I 1.1
I 0.6 I 0.7 Q8.0

Q 8.0 =

FBD Diagram

I 0.4 I 0.5 I 0.4 I 0.5 X X =

& >=1 & Q 8.0 =

STL

I 0.4 I 0.5 Q8.0


November 21, 2013

SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved

4/8

SIEMENS

Example:
1- Convert the Following Circuit Diagram to LAD. 2- Convert the LAD Diagram to STL.
I0.2 I0.4 I0.0 I0.1 I0.3 I0.5 I1.0

Answer:
1I0.6

I0.7

Q0.0

2-

SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved

5/8

November 21, 2013

SIEMENS

Exercise:
1- Convert the Following Circuit Diagram to STL.
I0.0 I0.2 I0.5 I0.7 I1.3 I0.1 I0.3 I0.6 I1.0 I1.5 I1.2 I1.4

I0.4 I1.1

I1.7

I1.6

Q0.0

SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved

6/8

November 21, 2013

SIEMENS

Set
The specified address is set to signal state "1" and remains set until another instruction resets the address.

Reset
The specified address is reset to signal state "0" and remains in this state until another instruction sets the address again.

I 0.0

I 0.1

I 0.2

Q 0.0

Q 0.0

(S)

LAD Diagram
I 0.3

(R)

I 0.0 I 0.1

I 0.2 & Q 0.1 S

FBD Diagram

>=1

Q 0.1 R

I 0.3

A I 0.0 A I 0.1 S Q 0.2

STL

O I 0.2 O I 0.3 R Q 0.2

SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved

7/8

November 21, 2013

SIEMENS

Setting/Reseting FlipFlop
Dominant Set M1.0 R I 0.5 S M1.0 I 0.4 R RS Q0.2 I 0.5 S A R A S A =
SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved

Setting/Reseting FlipFlop
Dominant Reset M1.1

I 0.4

RS

Q 0.2

I 0.4

SR

Q 0.3 Q

LAD Diagram

I 0.5

R
M1.1 I 0.4 S R A S A R A = I 0.4 M 1.1 I 0.5 M 1.1 M 1.1 Q 0.3
November 21, 2013

SR Q0.3

FBD Diagram
I 0.5 Q

Q I 0.4 M 1.0 I 0.5 M 1.0 M 1.0 Q 0.2

STL

8/8

SIEMENS

Midline Output Coil


It is an intermediate assignment element with assignment function

I 0.0 I 0.1 M0.6

I 0.3

I 0.4 NOT

M 1.0 Q 0.3

LAD Diagram

( )

( )

( )

I 0.0

& M0.6

I 0.1

&
I 0.3 I 0.4 M1.0 Q 0.3 =

FBD Diagram

STL

A A = A A A NOT = A = 9/8

I I M M I I M M Q

0.0 0.1 0.6 0.6 0.3 0.4 1.0 1.0 0.3 November 21, 2013

SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved

SIEMENS

SET
The SET instruction sets the RLO to "1" without preconditions

CLR
The CLEAR instruction sets the RLO to "0" without pre-conditions

NOT
The NOT instruction inverts the RLO.

NOt EXIST

LAD

NOt EXIST

LAD

I 0.0

I 0.1

Q0.0

NOT

( )

I 0.0 NOt EXIST

&

FBD

NOt EXIST

FBD

I 0.1

Q0.0 =

SET = M 0.4

STL

CLR = M 0.5

STL

A I 0.0 A I 0.1 NOT = Q0.0

SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved

10/8

November 21, 2013

SIEMENS

Negative Edge Detection

Positive Edge Detection

I 1.0 I 1.1

M1.0 N

M0.2

I 0.0 I 0.1

M0.0 P

M0.1

LAD Diagram
I 1.0

I 1.0 I 1.1

&

M1.1

M0.2

&

M1.0

M0.1

FBD Diagram

I 1.1

A A FN =

I 1.0 I 1.1 M1.1 M0.2

STL

A A FP =

I 1.0 I 1.1 M1.0 M0.1

SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved

11/8

November 21, 2013

SIEMENS

Positive Edge
(Positive Edge Detection) detects a signal change in the address (M0.1) from "0" to "1", and displays it as RLO = "1" after the instruction.

Examples 1:
OB1-Cycle

I 0.0 I 0.1

RLO

Negative Edge
(Negative Edge Detection) detects a signal change in the address (M1.1) from "1" to "0" and displays it as RLO = "1" after the instruction (such as at M 0.1) for one cycle.

M1.0 M1.1 M8.0 M8.1


Examples 2:

I 0.0 I 0.1 M1.0 M1.1


OB1-Cycle

M8.0 M8.1
SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved

12/8

November 21, 2013

SIEMENS

Unconditional Jump
In LAD/FBD, the label (M001) is entered as an identifier above the coil symbol or assignment symbol. In STL it comes after the Jump (JU) instruction. An unconditional jump instruction causes a program jump to a label regardless of the RLO.

Network 1

M001

( JMP )
LAD Diagram
Network 2 : : Network n

M001 M50.0 I 44.1 M99.7

( )
Jump Label
The label may be as many as four characters of which the first character must be a letter. Example: M001: A I 0.0
Network 1 JU M001

STL

Network 2 : : : : Network n M001: AN M50.0 AN I 44.1 = M99.7 13/8 November 21, 2013

SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved

SIEMENS Network 1

Conditional Jump
The "JC" conditional jump is only executed if the RLO is "1". The "JCN" conditional jump is only executed if the RLO is "0". Note: STL provides additional jump operations

I 0.0

I 0.1

M002 (JMP)

LAD Diagram

Network 2 : : Network n M002 M50.0 I 44.1 M99.7

( )
Network 1 A I 0.0 A I 0.1 JC M002 Network 2 : : : : Network n M002:

STL

AN M50.0 AN I 44.1 = M99.7 November 21, 2013

SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved

14/8

SIEMENS

Answer of Exercise 1:

Answer of Exercise 3:

SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved

15/8

November 21, 2013

SIEMENS

Answer of Exercise 2:

SIMATIC S7
SIEMENS LTD EGYPT 2007 All Rights Reserved

16/8

November 21, 2013