Digital Design with SM Charts

: : 2004.01.09

Contents

SM Charts properties
Derivation of SM Charts Implementation of the Dice game Alternative realizations for SM Charts using Microprogramming Linked State Machine

SM Charts properties

ASM (Algorithmic State Machine) Often used to design control units for digital systems Useful in the H/W design of digital systems Easier to understand the operation Leads directly to a hardware realization

Components of SM chart
Optional State code

xxx
State_name/ Output list

(true branch)

(false branch)

condition

Conditional Output list

(a) State box

(b) Decision box

(c) Conditional Output box

Example of an SM chart
One entrance path

S1/Z1Z2
Link Path a

One state

SM block

0 X1

1
Link Path b

Z3 Z4 0 X2 1

X3

Z5

n exit paths

Equivalent SM Blocks

S1/Z1 0 Z2 0 S2/ (a) X2 1 X1 1

Z2=1 if X1=0 S2 if X2=0 S3 if X2=1 1 0 Z2 S3/ S2/ X1

S1/Z1 0

X2

1 X1 0 Z2 S3/

Z2=1 if X1=0 S2 if X2=0 S3 if X2=1

(b)

Equivalent SM Charts for a combinational Network

S0/
S0/ 1 C 0 Z1 B 0 Z1 0 1 1 A 1

A+BC 0

(a)

(b)

Z1=A+A`BC=A+BC

SM Block with feedback

-Every valid combination of input variables must have exactly one exit path defined -No internal feedback within an SM block is allowed

S0/

S0/

x
1

x 1

(a) Incorrect

(b) Correct

Conversion of a state Graph to an SM chart

1/0 1/0 0/0

So/ Za
0/0

S1/ Zb
0/Z1

S2/ Zc

1/Z2

(a) State graph

00

S0/Za
Link 1 0

(b) Equivalent SM chart

01

S1/Zb
Link 2 0

S2/Zc
0

11

Link 3

Z1

Z2

Derivation of SM Charts

First, draw a block diagram of the system we are controlling

Next, define the required input and output signals to the control network Then, construct an SM char that tests the input signals and generates the proper sequence of output signals

Ex.1 Binary Multiplier

St : start, M : LSB, Ad : add, Sh : shift, K : last shift

EX1.SM Chart for Binary Multiplier

S0/
0

St

Load S1/
0

St : start, M : LSB, Ad : add, Sh : shift, K : last shift

1

Sh
0

Ad S2/Sh
1

K
1

S3/Done

EX1.VHDL for SM Chart

when 1 => if M=1 then --- M (state 1) Ad<=1 ; Nextstate<=2; else --- M Sh<=1; if K=1 then Nextstate<=3; --- K else Nextstate<=1; --- K end if end if when 2 => Sh<=1; --(state 2) if K=1 then Nextstate<=3; --- K else Nextstate<=1; --- K` end if when 3 => Done <= 1; Nextstate <= 0; --(state 3) end case; end process; process(CLK) begin if CLK = 1 then State <= Nextstate; --- update state on rising edge end if ; end process; End SMbehave ;

Entity Mult is port(CLK,St,K,M: in bit; Load,Sh,Ad,Done: out bit); End Mult; Architecture SMbehave of Mult is signal State, Nextstate : integer range 0 to 3; begin process(St, K, M, State) begin Load<=0 ; Sh<=0 ; Ad<=0 ; case State is when 0 => if St=1 then (state 0) --- St Load<=1; Nextstate<=1; else Nextstate<=0; --- St

EX2.Dice Game
Rule

The player wins if the sum is 7 or 11 The player loses if the sum is 2,3,12 otherwise, the sum is referred to as a point and roll again The second or subsequent, the player wins if the sum equals the point the player loses if the sum is 7, Otherwise, the player roll again until player wins or loses

EX2.Dice Game
Display Display DiceGame Module Rb 1-to-6 Counter 1-to-6 Counter Roll Reset

Adder Sum Test Logic

D7 D711 D2312

Control Win

Point Register

Comparator

Eq

Lose

Sp

<Block Diagram for Dice Game>

Flowchart for Dice Game

Roll dice Y N N Store sum in Point register
Sum = 2,3,12 Sum = 7 or 11

Roll dice Y N

Sum = Point

Sum = 7

Y Win Y N N Lose Y

Reset

Reset

SM chart for Dice Game

Roll 1

S0 / 0 Rb 1 S1 / Rb 0
D711

Press and Release

0
D2312

1
S3/Lose Reset 0

S0 : No button S1 : Button Pressed S2 : Win S3 : Lose

Roll 1 1 S2 / Win 1 Reset 0 0

0 Sp S4 / Rb 1 S5 / Rb 0 Eq

S4 : No button
S5 : Button Pressed

0
D7 1

Behavioral Model for Dice Game

Entity DiceGame is port (Rb, Reset, CLK: in bit; Sum: in integer range 2 to 12; Roll, Win, Lose: out bit); End DiceGame; Library BITLIB; Use BITLIB.bit_pack.all; Architecture DiceBehave of DiceGame is signal State, Nextstate: integer range 0 to 5 signal Point: integer range 2 to 12; signal Sp: bit; begin process(Rb, Reset, Sum, State) begin Sp<=0 ; Roll<=0 ; Win<=0 ; Lose<=0 ; case State is when 0 => if Rb=1 then Nextstate<=1; end if; when 1 => if Rb=1 then Roll<=1; elsif Sum =7 or Sum=11 then Nextstate<=2; elsif Sum=2 or Sum=3 or Sum=12 then Nextstate<=3; else Sp<=1 ; Nextstate<=4; end if;

Behavioral Model for Dice Game

when 2 => Win<=1; if Reset=1 then Nextstate<=0; end if ; when 3 => Lose<=1; if Reset=1 then Nextstate<=0; end if ; when 4 => if Rb=1 then Nextstate<=5; end if when 5 => if Rb=1 then Roll<=1; elsif Sum=7 then Nextstate<=3 ; else Nextstate<=4; end if; end case; end process; process(CLK) begin if rising_edge(CLK) then state<=Nextstate; if Sp=1 then Point<=Sum; end if; end if; end process; end DiceBehave;

Complete Dice Game

Entity Game is port(Rb, Reset,Clk : in bit; Win, Lose: out bit); end Game;

component Dicegame port(Rb, Reset,Clk : in bit; Sum : out integer range 2 to 12; Roll, Win, Lose : out bit); end component; signal roll1 : bit; signal sum1: integer range 2 to 12; begin Dice:Dicegame port map(Rb,Reset,Clk,sum1,roll1,Win,Lose); Counter port map(Clk,roll1,sum1); end Play1;

Architecture Play of Game is component Counter port(Clk, Roll : in bit; Sum : out integer range 2 to 12); end component;

Implementation of Dice game

Rb Reset D711 D7 D2312 Eq Win Lose Roll Sp

PLA
C

C+ B+

D Q CK D Q CK D Q CK

B
A

A+

Clock

<PLA Realization of Dice Game Controller>

Realization of SM Chart - PLA Table for Dice Game

ABC 1 000 Rb 0 Reset D7 D711 D2312 Eq A+ 0 B+ 0 C+ 0 Win 0 Lose 0 Roll 0 Sp 0

2
3 4 5 6 7 8 9

000
001 001 001 001 010 010 011

1
1 0 0 0 -

0 1 1

0 0 1 -

0 1 -

0
0 1 0 0 0 0 0

0
0 0 1 1 1 0 0

1
1 0 1 0 0 0 0

0
0 0 0 0 1 1 0

0
0 0 0 0 0 0 1

0
1 0 0 0 0 0 0

0
0 1 0 0 0 0 0

10
11 12 13 14 15 16 17 18

011
100 100 101 101 101 101 110 111

0 1 0 0 0 1 -

0
-

0 1 -

0 0 1 -

0
1 1 1 0 0 1 -

1
0 0 0 1 1 0 -

1
0 1 0 1 0 1 -

0
0 0 0 0 0 0 -

1
0 0 0 0 0 0 -

0
0 0 0 0 0 1 -

0
0 0 0 0 0 0 -

Maps Derived from the previous table

A+ = ABCRbD711D2312+AC+ARb+AD7Eq, B+ = ABCRb(D711+D2312)+Breset+ACRb(Eq+D7) C+ = BRb+ABCD711D2312+BCReset+ACD7Eq, Win = BC, Lose = BC, Roll = BCRb

Sp = ABCRbD711D2312

Data Flow Model for Dice Game

architecture Dice_Eq of DiceGame is signal Sp, Eq, D7, D711, D2312 : bit : =0; signal DA, DB, DC, A, B, C, : bit : =0; signal Point : integer range 2 to 12 ; begin process(CLK) begin if rising_edge(CLK) then A<=DA; B<=DB; C<=DC; if Sp=1 then Point<=Sum; end if; end if end process ;

Data Flow Model for Dice Game

Win <=B and not C: Lose <=B and C; Roll <= not B and C and Rb; Sp <= not A and not B and C and not Rb and not D711 and not D2312; D7 <=1 when Sum=7 else 0; D711 <=1 when (Sum=11) or (Sum=7) else 0; D2312<=1 when (Sum=2) or (Sum=3) or (Sum=12) else 0; Eq <=1 when Point=Sum else 0; DA <= (not A and not B and C and not Rb and not D711 and not D2312) or (A and not C) or (A and Rb) or (A and not D7 and not Eq) DB <=( (not A and not B and C and not Rb) and (D711 or D2312) ) or (B and not Reset) or ( (A and C and not Rb) and (Eq or D7) ); DC <= (not B and Rb) or (not A and not B and C and not D711 and D2312) or (B and C and not Reset) or (A and C and D7 and not Eq); End Dice_Eq;

Alternative realizations for SM Charts using Microprogramming

<Control Network Using an Input MUX to Select the Next State>

PLA or ROM or PAL

Register Inputs

TEST NSF NST OUTPUT

MUX1

MUX2

The only input to PLA come from state register

Test controls MUX1 with inputs

NSF or NST decided by inputs BOOLEAN (NST: Next State True) Must have only Moore outputs (Outputs depend on only current state)

Linked State Machine

A sequential machine becomes large and complex, Desirable to divide the machine into several smaller machines linked together. Each of the smaller machines is easier to design and implement.
Machine A (calling machine) Machine B (called machine)

SOME STATES

IDLE 0

ZA SA / ZA 0 1 OTHER STATES

ZB 1 OTHER STATES

SB/ ZB