Full Adder

A full adder is a combinational circuit that forms the arithmetic sum of three bits. It consists of three inputs and two outputs. Applications: Multipliers Compressors Comparators and Parity checkers.
Ref[1]: Morris Mano, Digital Design With an Introduction to the Verilog HDL FIFTH EDITION

Full Adder Truth Table and K-map

Ref[1]: Morris Mano, Digital Design With an Introduction to the Verilog HDL FIFTH EDITION

Basic Full Adder Circuit

Ref[1]: Morris Mano, Digital Design With an Introduction to the Verilog HDL FIFTH EDITION

Full Adder with Two Half Adders and OR Gate

Ref[1]: Morris Mano, Digital Design With an Introduction to the Verilog HDL FIFTH EDITION

Implementation of Basic Full Adder

Ref[2]: Enhanced Ground Bounce Noise Reduction In a Low Leakage 90nm 1-Volt CMOS Full Adder Cell

Conventional FA with Pass Transistor

Ref[2]

GDI(Gate Diffusion Input)

GDI Implements wide range of complex logic functions using only two transistors. It looks like CMOS inverter. The GDI cell contains three inputs: G(common gate input of nMOS and pMOS), P (input to the source /drain of pMOS), and N (input to the source/drain of nMOS). 2) Bulks of both nMOS and pMOS are connected to N or P (respectively), so it can be arbitrarily biased at contrast with a CMOS inverter.

Both F1 and F2 are complete logic families (allows realization of any possible twoinput logic function). F1 is the only GDI function that can be realized in a standard p-well CMOS process, because the bulk of any nMOS is constantly and equally biased. When N input is driven at high logic level and P input is at low logic level, the diodes between NMOS and PMOS bulks to Out are directly polarized and there is a short between N and P, resulting in static power dissipation and Vout=0.5Vdd.

 In PTL circuit design is the problem of swing degradation. swing restoration in GDI circuits under constraints of area (power) and circuit frequency (delay). The simplest method of swing restoration is to add a buffer stage after every GDI cell. This will certainly prevent the voltage drop, but the payment will be in additional area, delay, and power dissipation, which makes this method highly inefficient. Note that our approach to swing restoration is rather simple;

several points have to be emphasized concerning the buffer insertion topology in GDI.
Buffer insertion has to be considered only in the case of linking GDI cells through diffusion inputs. No buffers are needed before gate inputs of GDI cells. Due to this feature, the mixed path topology can be used as an efficient method for buffer insertion. It allows one to reduce the number of buffers by intermittently involving diffusion and gate inputs in a given signal path The designer should check the tradeoff between buffer insertion and delay, area, and power consumption to achieve an efficient swing restoration.

Basic Gates using Different techniques

Ref[3]: Gate-Diffusion Input (GDI): A Power-Efficient Method for Digital Combinatorial Circuits

Full Adder using GDI

Ref[4]: Design and Performance Analysis of 1 bit Full Adder using GDI Technique in Nanometer Era

Modified GDI Based Full Adder

Ref[4]: Design and Performance Analysis of 1 bit Full Adder using GDI Technique in Nanometer Era

References
1. Morris Mano, Digital Design With an Introduction to the Verilog HDL FIFTH EDITION. 2. Enhanced Ground Bounce Noise Reduction In a Low Leakage 90nm 1-Volt CMOS Full Adder Cell. 3. Gate-Diffusion Input (GDI): A Power-Efficient Method for Digital Combinatorial Circuits. 4. Design and Performance Analysis of 1 bit Full Adder using GDI Technique in Nanometer Era.