Annushapriya.

S /
 Interfacing with 8085
Interfacing??
Method or piece of equipment for
interconnecting units or systems which may not be
directly compatible

M.P.U M.P.U

RD WR
Programmable Programmable
Interface Device Interface Device

Peripherals Peripherals
(Keyboard, mouse) (Printer)

Annushapriya.S /
8255-Programmable Peripheral
Interface (PPI)
Characteristics - 8255

• Programmable parallel I/O device

• 40 pin IC
Block diagram - 8255

Ports

Data Bus
Buffer

Control
Logic
Annushapriya.S /
 Port A (8- bit parallel port)

Ports Port B (8- bit parallel

port)
Port Cupper
(4 - bit
Port C Port)
Port Clower
Annushapriya
.S / ECE
(4 - bit
Port)
 Data Bus Buffer

• 8- bit Data line

• Bi-directional
• D7 – D0

Annushapriya.S /
 Control Logic

• Consists of 6 Lines
( RD, WR, RESET, CS, A0, A1)

1. RD (Read)

• Enables read operation

• Active low
• Logic 0 – M.P.U. reads data from a selected I/O
port of 8255

Annushapriya.S /
 1. WR (Write)

• Enables write operation

• Active low
• Logic 0 – M.P.U. writes data into a selected I/O port
of 8255 or control register

1. RESET

• Clear Control Register

• Active high
• Sets all ports in input mode

Annushapriya.S /
 1. CS (Chip Select)
• Master chip select

• A0 Specify one of I/O ports on control

register
• A1

8255 – Chip Select Logic

CS A1 A0 Selected
0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control Reg.
1 X X Not selected
Annushapriya.S /
 Block diagram - 8255

Annushapriya.S /
 A1 Port A (80 H)
A7 A0
A6
A5 CS
A4 Port C (82 H)
A3 8255
A2 RD
WR Port B (81 H)
RESET

I/O Port Address

cs HEX. Ports
A7 A6 A5 A4 A3 A2 A1 A0 Address
1 0 0 0 0 0 0 0 80 H Port A
1 0 0 0 0 0 0 1 81 H Port B
1 0 0 0 0 0 1 0 82 H Port C
1 0 0 0 0 0 1 1 83 H Control Register
Annushapriya.S /
 Control Word
•Contents of Control Register is known as Control
Word
• Specify I/O functions for each port
• 8-bit length

Control Register

D7 D6 D5 D4 D3 D2 D1 D0

D7  0 (BSR Mode)
D7  1 (I/O Mode)

Annushapriya.S /
BSR(Bit Set Reset) Mode:
• Port C operates in bit set or reset mode
• It doesn't affect Port A or Port B

I/O Mode:
•Mode 0  All ports (A, B, C) are simple I/O ports
•Mode 1  Handshake mode where Ports A &/or B
use bits from Port C as handshake
•Mode 2  Port A is used for bi-directional data
transfer engaging handshake signals
from Port C; Port B can be set up either
in Mode 0 or Mode 1

Annushapriya.S /
• While ports A, B, and C are used for
I/O data, it is the control register that
must be programmed to select the
operation mode of the three ports A,
B, and C. The ports of the 8255 can
be programmed in any of the
following modes
• It has three modes of operation

13
• Simple I/O mode
• Any of the ports A, B, CL, and CU can
be programmed as input or output
• All bits are out or all are in
(there is no control of individual bits)

14
 Mode 1

• Simple I/O with handshaking

capabilities
• Ports A and B can be used as input or
output ports with handshaking
capabilities
• Handshaking signals are provided by
the bits of port C
(the device provides the handshaking
signals)

15
• Bidirectional port A with handshaking
capabilities
• Port A can be used as a bidirectional
I/O port with handshaking
capabilities whose signals are
provided by port C.
(the device provides the handshaking
signals)

16
• A unique feature of port C is that the
bits can be controlled individually. BSR
mode allows one to set to high or low
any of PC0 to PC7 as shown in Figure
below.

17
• Program PC4 of the 8255 in the following Figure
to generate a pulse of 50 ms with 50% duty
cycle.

18
• To program the 8255 in BSR mode,
• bit D7 of the control word must be low.
• For PC4 to be high, we need a control word of
‘0xxx1001".
• Likewise, for low we would need “0xxx1000" as
the control word.
• The x's are for "don't care" and generally are set
to zero.

MVI A,09H ; load the control byte (PC4=1)

OUT 93H ;set PC4 to high, sent to control reg
CALL DELAY ;time for the high part of pulse
MVI A,08H ;load the control byte (PC4=0)
OUT 93H ;set PC4 to low, sent to control reg

19
CALL DELAY ;time for the low part of pulse
• Handshaking refers to the process
of communicating back and forth
between two intelligent devices
• 8255 handles handshaking
signals
(a powerful built in features of the 8255)
• Printers are good example for a
device with handshaking capabilities

22
 8 Printe
255 r
PA D0 – D7

PC7 STROBE

PC6 ACK

23
• A byte of data is presented to the data
bus of the printer.
• The printer is informed of the presence of
a byte of data to be printed by activating
its STROBE input signal.
• Whenever the printer receives the data it
informs the sender by activating an
output signal called ACK (acknowledge).
• The ACK signal initiates the process of
providing another byte of data to the
printer.

24
• The 8255 can be programmed to
receive data through ports A and B
using handshaking signals through
port C
• The signals are as follows:

25
Inputting data with handshaking
signals (mode 1)

26
From the fig,
 A and B are configured as input ports
 PORT A uses upper three signals PC3,PC4 and PC5.
PORT B uses lower three signals PC0,PC1 and PC2.
• Active-low input signal.
• When an external peripheral device
provides a byte of the data to an
input port (A or B), it informs the
8255 through the STB pin that
PERIPHERAL HAS TRANSMITTED and
it can load (latch in) the data into its
internal register
• This signal goes low (active), stays
low for a time, and goes back high.

28
The amount of time it stays low
 The 8255 in
response to
strobe generates
IBF and INTR
STB
• Active-high output signal.
• In response to STB, the 8255 latches
into its internal register the data
present at PA0-PA7 or PB0-PB7, and
through IBF indicates that it has
latched the data, but it has not been
read by the CPU yet
• To get the attention of the CPU to
read the data, IBF activates INTR
(sets it high).

30
• Active-high output signal to interrupt the
CPU.
• If INTE =1 , STB’=1, IBF=1
• When IBF goes active, INTR is activated
(set to high) to inform the CPU that there is
a byte of data in the 8255.
• Either an interrupt or polling the status
word can be used to read the data from
port A or B.
• It is only when the CPU reads the data by
activating the RD (going low) signal of the
8255 that INTR becomes inactive (the
falling edge of RD makes INTR go low)

31
• The RD signal from the CPU is of limited
duration and when it goes high, the 8255
in turn makes IBF inactive by setting it
low.
• IBF informs the peripheral device that the
byte of data was latched by the 8255 and
transferred to the CPU as well.
• By receiving IBF, the external device
knows it can send another byte to the
8255's port A or port B.
• Then it sets low STB, and the process is
repeated.
• Notice that INTR is set to one when all
three signals STB, IBF, and INTE are high.

32
• The CPU services various devices. There are two ways for
the CPU to provide service to those devices: interrupts and
polling.
• In the interrupt method, whenever any device needs its
service, the device informs the CPU by sending it an
interrupt signal. The CPU interrupts whatever it is doing and
serves the request for service.
• In polling, the CPU continuously monitors a status condition
and when the conditions are met it will perform the service.
• The advantage of interrupts is that the CPU can serve many
devices (of course, not all at the same time). Each device
receives service from the CPU based on the priority
assigned to it. It can also ignore (mask) a device request for
service.
• The disadvantage of interrupts is that they require much
more hardware and software.
• In contrast, polling is cheap and requires minimal software,
but it ties down the CPU. To avoid tying down the CPU,
interrupts are the preferred choice.

33
• INTE (interrupt enable)
• An internal flip-flop can be used to enable
or disable (mask) INTR generation. It is
controlled by PC4 and PC2 in BSR mode.
• To control INTEa and INTEb, use PC4 and
PC2, respectively.
• Status word
• To allow implementation of polling, the
status of the handshaking signals provided
by port C can be checked by reading port
C.

34
• As shown, A and B can be used as
output ports to send data to a device
with handshaking signals.
• The handshaking signals for both
ports A and B are provided by the
bits of port C.

35
Outputting data with handshaking signals (mode 1)

36
• Active-low signal going out of PC7
• Indicate that the CPU has written a
byte of data into port A, so the
receiving peripheral device can read
it
• OBFa must be connected to
STROBE of the receiving equipment
(such as a printer)

37
• Active-low signal (Has limited
duration)
• Received at PC6 of the 8255
• Indicates that the data at port A has
been picked up by the receiving
device
• The 8255 in turn makes OBFa high,
to indicate that the data at the port
is old data

38
• OBFa will not go low until the CPU
• Active-high signal coming out of PC3
• Activated by the rising edge of ACK
which is active for a short period of
time
• Signal on INTRa can be used to get
the attention of CPU (printer has
received the last byte and is ready to
receive another one)
• INTRa interrupts the CPU to write

39
the next byte to port A to be printed.
• 8255 can disable INTRa to prevent it
from interrupting the CPU
• INTEa is an internal flip-flop designed
to mask (disable) INTRa
• INTEa can be set or reset through
port C in BSR mode since the INTEa
flip-flop is controlled through PC6
• INTEb is controlled by PC2 in BSR
mode

40
• 8255 enables monitoring the status
of signals INTR, OBF, and INTE for
both ports A and B
• This is done by reading port C into
the accumulator and testing the bits
• This feature allows the
implementation of polling

41
• The CPU services various devices. There are two ways for
the CPU to provide service to those devices: interrupts and
polling.
• In the interrupt method, whenever any device needs its
service, the device informs the CPU by sending it an
interrupt signal. The CPU interrupts whatever it is doing and
serves the request for service.
• In polling, the CPU continuously monitors a status condition
and when the conditions are met it will perform the service.
• The advantage of interrupts is that the CPU can serve many
devices (of course, not all at the same time). Each device
receives service from the CPU based on the priority
assigned to it. It can also ignore (mask) a device request for
service.
• The disadvantage of interrupts is that they require much
more hardware and software.
• In contrast, polling is cheap and requires minimal software,
but it ties down the CPU. To avoid tying down the CPU,
interrupts are the preferred choice.

42