CSCE 212 Chapter 2: Instruction Set Architecture

Instructor: Jason D. Bakos

Lecture Outline
Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O

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Instruction Set Architecture

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Instruction Set Architecture

Instruction Set Architecture:
1. abtraction that hides the low-level details of a processor from the user 2. the interface between the hardware and software 3. everything you need to know to use the processor:
instruction set instruction representations addressing modes etc

Families of processors are defined by their ISA:

Sun Sparc Intel IA-32 MIPS IBM 360 Motorola/IBM PowerPC

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ISAs Today

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Processor Classes

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MIPS ISA
100 million MIPS processors manufactured in 2002 MIPS processors used in:
Products from ATI, Broadcom, NEC, Texas Instruments, Toshiba SGI workstations Series2 TiVo Windows CE devices Cisco/Linksys routers Nintendo 64 Sony Playstation 1, PS2 (Emotion), PSP Cable boxes

Competes against XScale/ARM for cell phones

John L. Hennessy (Stanford, 1981)

1984: MIPS Computer Systems R2000 (1985), R3000 (1988), R4000 (64-bit, 1991) SGI acquisition (1992) => MIPS Technologies Transition to licensed IP: MIPS32 and MIPS64 (1999) Heavyweight embedded processor

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Lecture Outline
Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O

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MIPS Microarchitecture

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RISC vs. CISC

Design philosophies for ISAs: RISC vs. CISC
CISC = Complex Instruction Set Computer RISC = Reduced Instruction Set Computer

Tradeoff:
Execution time = instructions per program * cycles per instruction * seconds per cycle

Problems with CISC:

Compilers Off-chip memory references Complex control, unbalanced instruction set made parallelizing difficult

MIPS is the first implementation of a RISC architecture

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RISC vs. CISC

MIPS R2000 ISA

Designed for use with high-level programming languages

Easy for compilers Example: mapping IA32 instruction CRC32 (accumulate CRC32 value)

Balance amount of work per instruction (pipelining) Load-store machine

Force user to minimize off-chip accesses

Fixed instruction width (32-bits), small set of uniform instruction encodings

Reduce implementation complexity

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Lecture Outline
Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O

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MIPS Instruction Types

MIPS instructions fall into 5 classes:
Arithmetic/logical/shift/comparison Control instructions (branch and jump) Load/store Other (exception, register movement to/from GP registers, etc.)

Three instruction encoding formats:

R-type (6-bit opcode, 5-bit rs, 5-bit rt, 5-bit rd, 5-bit shamt, 6-bit function code)

I-type (6-bit opcode, 5-bit rs, 5-bit rt, 16-bit immediate)

J-type (6-bit opcode, 26-bit pseudo-direct address)

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Partial MIPS Instruction Set (see Appendix. A)

Arithmetic R-type: Arithmetic I-type: Logical R-type: Logical I-type: Compare R-type: Compare I-type: Shift R-type: Load/Store I-type: Branch I-type: Jump J-type: Jump R-type: OS support: Multiply/divide: add, addu, sub, subu addi, addiu and, or, nor, xor andi, ori, xori slt, sltu slti, sltiu sll, sllv, srl, srlv, sra, srav lui, lw, lh, lhu, lb, lbu, sw, sh, sb j, jal jr, jalr syscall mult, multu, div, divu

beq, bne, bgez, bgezal, bgtz, blez, blezal, bltz

result held in 2 special registers (hi,lo)

Floating-point instructions
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MIPS Registers
32 x 32-bit general purpose integer registers Some have special purposes These are the only registers the programmer can directly use

$0 => constant 0 $1 => $at (reserved for assembler) $2,$3 => $v0,$v1 (expression evaluation and results of a function) $4-$7 => $a0-$a3 (arguments 1-4) $8-$15 => $t0-$t7 (temporary values) Used when evaluating expressions that contain more than two operands (partial solutions) Not preserved across function calls $16-$23 => $s0->$s7 (for local variables, preserved across function calls) $24, $25 => $t8, $t9 (more temps) $26,$27 => $k0, $k1 (reserved for OS kernel) $28 => $gp (pointer to global area) $29 => $sp (stack pointer) $30 => $fp (frame pointer) $31 => $ra (return address, for branch-and-links)

Program counter (PC) contains address of next instruction to be executed

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Design Considerations
Most arithmetic instructions have 3 operands simplifies the hardware
Limits the number of datapaths on the processor

Limiting to 32 registers speeds up register access time

For memories, smaller is faster Influences clock cycle time

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Arithmetic
Arithmetic (R-type) instructions
add a,b,c sub a,b,c a=b+c a=b-c

C code:
f = (g + h) (i + j)

to
add t0,g,h add t1,i,j sub f,t0,t1

t0, t1, f, g, h, i, j must be registers

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Registers
f, g, h, i, j in $s0, $s1, $s2, $s3, $s4

To
add $t0,$s1,$s2 add $t1,$s3,$s4 sub $s0,$t0,$t1

Similar instructions:
addu, subu and, or, nor, xor slt, sltu

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Encoding R-type Instructions

ADD $2, $3, $4

R-type A/L/S/C instruction Opcode is 0s, rd=2, rs=3, rt=4, func=100000 000000 00011 00100 00010 00000 100000
0000 0000 0110 0100 0001 0000 0010 0000 0000 0000 0110 0100 0001 0000 0010 0000 00641020

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Immediate Instructions
Second operand is a 16-bit immediate Signed (-32,768 to 32,767) or unsigned (0 to 65,535) Encoded with I-type addi $s0, $t0, -4

Similar I-type instructions:

addiu andi, ori, xori lui

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Encoding I-Type Arithmetic/Logical/Compare

ADDI $2, $3, 12

I-type A/L/S/C instruction Opcode is 001000, rs=3, rt=2, imm=12 001000 00011 00010 0000000000001100

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Load Upper Immediate

Need more than 16 bits?

Example:
Initialize register $t0 with 1234567816 lui $t0, 1234 addi $t1, $0, 5678 or $t0, $t0, $t1

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Shift Instructions
Shift left-logical:
001010012 by 210 => 101001002 Multiply 4110 by 2210 = 16410

Shift right-logical:
001010012 by 210 => 000010102 Divide 4110 by 2210 (round down) = 1010

Shift right-arithmetic
111101012 by 210 => 111111012 Divide -1110 by 2210 (round down) = -310

Amount (0-31) is encoded in SHAMT field for SLL, SRL, SRA Held in a register (rs field) for SLLV, SRLV, SRAV

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Load and Store

Memory units:
word (32 bits, 4 bytes) halfword (16 bits, 2 bytes) byte (8 bits)

Assume f, g, h, i, j are stored as words and contiguously

la lw lw lw lw sw $t2, f $s1,4($t2) $s2,8($t2) $s3,12($t2) $s4,16($t2) $s0,0($t2)

Similar instructions:
lh, lhu, lb, lbu sh, sb

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Encoding I-Type Load/Store

SW $2, 128($3)
I-type memory address instruction Opcode is 101011, rs=00011, rt=00010, imm=0000000010000000 101011 00011 00010 0000000010000000

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Branch Instructions
Branch and jump instructions are required for program control
if-statements loops procedure calls

Unconditional branch
b <label>

Conditional branch
beq, bgez, bgezal, bgtz, blez
and-link variants write address of next instruction into $31 (only if branch is taken) Branch targets are 16-bit immediate offset (offset in words)

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Encoding I-Type Branch

BEQ $3, $4, 4

I-type conditional branch instruction Opcode is 000100, rs=00011, rt=00100, imm=4 (skips next 4 instructions) 000100 00011 00100 0000000000000100

Note:
bltz, bltzal, bgez, bgezal all have opcode 1, func in rt field

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Jump Instructions
Unconditional branch Two types: R-type and J-type
JR $31 JALR $3
R-type jump instruction Opcode is 0s, rs=3, rt=0, rd=31 (by default), func=001001 000000 00011 00000 11111 00000 001001

J 128
J-type pseudodirect jump instruction Opcode is 000010, 26-bit pseudodirect address is 128/4 = 32 000010 00000000000000000000100000

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MIPS Addressing Modes

MIPS addresses register operands using 5-bit field
Example: ADD $2, $3, $4

MIPS addresses branch targets as signed instruction offset

relative to next instruction (PC relative) in units of instructions (words) held in 16-bit offset in I-type Example: BEQ $2, $3, 12

Immediate addressing
Operand is help as constant (literal) in instruction word Example: ADDI $2, $3, 64

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MIPS Addressing Modes (cont)

MIPS addresses jump targets as register content or 26-bit pseudo-direct address
Example: JR $31, J 128

MIPS addresses load/store locations

base register + 16-bit signed offset (byte addressed)
Example: LW $2, 128($3)

16-bit direct address (base register is 0)

Example: LW $2, 4092($0)

indirect (offset is 0)
Example: LW $2, 0($4)

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Integer Multiply and Divide

mult $2, $3
result in hi (32 bits) and lo (32 bits) mul $2, $3, $4 is psuedo (low 32 bits) madd $2, $3 multiply and accumulate in hi and lo

div $2, $3
quotient in lo and reminder in hi div $2, $3, $4 is psuedo (quotient)

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Pseudoinstructions
Some MIPS instructions dont have direct hardware implementations
Ex: abs $2, $3
Resolved to:
bgez $3, pos sub $2, $0, $3 j out pos: add $2, $0, $3 out:

Ex: rol $2, $3, $4

Resolved to:
addi $1, $0, 32 sub $1, $1, $4 srlv $1, $3, $1 sllv $2, $3, $4 or $2, $2, $1

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Lecture Outline
Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O

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Complex Arithmetic Example

z=(a*b)+(c/d)-(e+f*g); lw $s0,a lw $s1,b mult $s0,$s1 mflo $t0 lw $s0,c lw $s1,d div $s0,$s1 mflo $t1 add $t0,$t0,$t1 lw $s0,e lw $s1,f lw $s2,g mult $s1,$s2 mflo $t1 add $t1,$s0,$t1 sub $t0,$t0,$t1 sw $t0,z

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If-Statement
if ((a>b)&&(c==d)) e=0; else e=f;
lw $s0,a lw $s1,b bgt $s0,$s1,next0 b nope lw $s0,c lw $s1,d beq $s0,$s1,yup lw $s0,f sw $s0,e b out xor $s0,$s0,$s0 sw $s0,e

next0:

nope:

yup:

out:

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For Loop
for (i=0;i<a;i++) b[i]=i;
lw $s0,a loop0: loop1:

out:

li $s1,0 blt $s1,$s0,loop1 b out sll $s2,S1,2 sw $s1,b($s2) addi $s1,$s1,1 b loop0

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Pre-Test While Loop

while (a<b) { a++; }
lw $s0,a lw $s1,b blt $s0,$s1,loop1 b out addi $s0,Ss0,1 sw $s0,a b loop0

loop0: loop1:

out:

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Post-Test While Loop

do { a++; } while (a<b);
lw $s0,a lw $s1,b addi $s0,$s0,1 sw $s0,a blt $s0,$s1,loop0

loop0:

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Complex Loop
for (i=0;i<n;i++) a[i]=b[i]+10;

loop:

test:

li $2,$0 lw $3,n sll $3,$3,2 la $4,a la $5,b j test add $6,$5,$2 lw $7,0($6) addi $7,$7,10 add $6,$4,$2 sw $7,0($6) addi $2,$2,4 blt $2,$3,loop

# # # # #
# # # # # # #

zero out index register (i) load iteration limit multiply by 4 (words) get address of a (assume < 216) get address of b (assume < 216)
compute address of b[i] load b[i] compute b[i]=b[i]+10 compute address of a[i] store into a[i] increment i loop if test succeeds

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Lecture Outline
Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O

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SPIM

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SPIM
ASM file must be edited with text editor Must have main label Must jr $31 at end Use .data and .text to specify sections

Load source file into SPIM Run, step, or use breakpoints

Appendix A is good reference In-class example: ASCII to binary conversion
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Example Code
mystr: .data .asciiz "2887"

main:

loop:

done:

.text addi $s0,$0,0 # addi $s1,$0,0 # addi $s3,$0,10 # lb $s2,mystr($s1) # beqz $s2,done # mul $s0,$s0,$s3 # addi $s2,$s2,-48 # add $s0,$s0,$s2 # addi $s1,$s1,1 # b loop # jr $31 #

initialize $s0 (current value) initialize $s1 (string index) initialize $s3 (value 10) load a character from string exit if it's the NULL character multiply current value by 10 subtract 48 from character (convert to binary) add converted value to current value add one to index loop return to OS

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Lecture Outline
Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O

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Procedures
JAL, JALR, and BGEZAL are designed to call subroutines Return address is linked into $31 ($ra) Need to:
save the return address on a stack to save the return address save the state of the callees registers on a stack have a place for arguments have a place for return value(s)

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Memory Allocation

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The Stack
Stack is designed to hold variable-sized records Stack grows down

Normally the old $fp must be stored in the AR to pop Dont need $fp for fixed-sized ARs

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A Simple Procedure Calling Convention

Caller:
Place arguments in $a0 - $a3 (limit to 4) Jump-and-link or branch-and-link to subroutine

Callee:
Pushes an activation record onto the stack (decrement $sp) Save the return address ($ra) on the AR Save registers $s0 - $s7 on the AR Perform computation Save return values to $v0 and $v1 Restore $s0 - $s7 Restore $ra JR $ra

Caller:
Reads $v0 and $v1 and continues

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Notes
This convention:
Limited to 4 arguments and 2 return values (bad!) Doesnt save $t0 - $t9, $v0 - $v1, and $a0 - $a3 (bad!) Doesnt allow (variable-size) space on the AR for argument list (saves regs) Doesnt allow (variable-size) space on the AR for callees local variables (bad!) Doesnt allow space on the AR for return value (saves regs) Fixed AR size (good!) Doesnt require the caller to prepare and/or teardown the AR (good!)

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Stack Example

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A Simple Procedure Calling Convention

comp: add $s0,$s1,$s2 jal fact
$sn for comps caller $ra for comp

$sp

fact: add $sp,$sp,-36 sw $s0,0($sp) sw $s1,4($sp) sw $ra,32($sp) lw $s0,0($sp) lw $s1,4($sp)

$sp+36 $sp

$sn for comp caller $ra for fact $sn for comps caller $ra for comp

$sp+36

lw $ra,32($sp)
add $sp,$sp,36 jr $ra (instruction after jal fact)

$sp+72

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Example
fact: slti beq addi jr L1: addi sw sw addi jal lw lw addi mul jr $t0,$a0,3 $t0,$zero,L1 $v0,$zero,2 $ra $sp,$sp,-8 $ra,4($sp) $a0,0($sp) $a0,$a0,-1 fact $a0,0($sp) $ra,4($sp) $sp,$sp,8 $v0,$a0,$v0 $ra # # # # # # # # # # # # # # test for n < 3 if n >= 1, go to L1 return 2 return allocate space for 2 items save return address save argument set argument to n-1 recurse restore original argument restore the return address pop 2 items return value = n * fact(n-1) -glad we saved $a0 go back to caller

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Lecture Outline
Instruction Set Architectures MIPS ISA MIPS Instructions, Encoding, Addressing Modes MIPS Assembly Examples SPIM Procedure Calling Conventions I/O

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I/O
I/O is performed with reserved instructions / memory space Performed by the operating system on behalf of user code Use syscall instruction Call code in $v0 and argument in $a0 Return value in $v0 (or $f0) SPIM services:

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Example
str: .data .asciiz the answer =

.text li $v0,4 la $a0, str syscall li $v0,1 la $a0,5 syscall

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Example Exercise
Copy words from the address in register $a0 to the address in register $a1, counting the number of words in $v0 Stops when 0 is read Do not preserve $a0, $a1, $v0 Terminating word should be copied but not counted addi $v0, $zero, 0 lw $v1, 0($a0) sw $v1, 0($a1) addi $a0, $a0, 4 addi $a1, $a1, 4 beq $v1, $zero, loop

loop:

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Example Exercise
Translate from binary to assembly: AE0B0004 8D080040 Change MIPS:
8 registers 10 bit immediate constants What is the new size of R and I type instructions?

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Example Exercise
field

31-i bits

i-j bits

j bits

Extract the bits from field in register $t0 and place them into the least significant bits of $t1 i = 22, j = 5

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