Chapter 12

Digital Integrated Circuits
A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic
Semiconductor Memories
December 20, 2002
Digital Integrated Circuits2nd
Memories
Chapter Overview
Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies
Memories
Semiconductor Memory Classification

Read-Write Memory Non-Volatile Read-Write Memory EPROM E2PROM FLASH Read-Only Memory
Random Access
Non-Random Access FIFO LIFO Shift Register CAM
Mask-Programmed
Programmable (PROM)
SRAM DRAM
Memories
Memory Timing: Definitions
Memories
Memory Architecture: Decoders

M bits S0 S1 S2 S0 A0 A1 M bits Word 0 Word 1 Word 2 Storage cell Word 0 Word 1 Word 2 Storage cell
words SN 2 2 N
SN 2
1
A K2 Word N 2 2 Word N 2 1
Decoder Word N 2
Word N 2 1 K 5 log2N
Input-Output ( M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals
Input-Output ( M bits) Decoder reduces the number of select signals
K = log2N
Memories
Array-Structured Memory Architecture

Problem: ASPECT RATIO or HEIGHT >> WIDTH
Amplify swing to rail-to-rail amplitude
Selects appropriate word
Memories
Hierarchical Memory Architecture
Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings Digital Integrated Circuits2nd
Memories
Block Diagram of 4 Mbit SRAM

Clock generator Z -address buffer X -address buffer Predecoder and block selector Bit line load
128 K Array Block Subglobal row decoder SubglobalGlobal row decoder row decoder Block 30 Block 31 Block 1
Transfer gate Column decoder
Sense amplifier and write driver
Local row deco

X -address buffer
CS, WE buffer
I/O buffer
x1/x4 controller
Y -address buffer
[Hirose90]
Memories
Contents-Addressable Memory
I/O Buffers
Data (64 bits)
I/O Buffers I/O Buffers
Commands
Comparand
Mask
Address Decoder
Control Logic R/W Address (9 bits)
CAM Array 2 words 3 64 bits

9
Validity Bits 9 2 Priority Enc Validity Bits Address Decoder 9 2 Address Decoder Priority Enc
Priority Encoder
Commands Commands
29 Validity Bits
Memories
Memory Timing: Approaches
DRAM Timing Multiplexed Adressing
SRAM Timing Self-timed
Memories
Read-Only Memory Cells

BL VDD WL WL WL BL BL
BL WL WL
BL
BL WL
0
GND Diode ROM MOS ROM 1 MOS ROM 2
Memories
MOS OR ROM
BL [0] BL [1] BL [2] BL [3]
WL [0]
V DD WL [1]
WL [2]
V DD WL [3]
V bias Pull-down loads
Memories
MOS NOR ROM

V DD Pull-up devices
WL [0]
GND WL [1]
WL [2] GND WL [3]
BL [0]
BL [1]
BL [2]
BL [3]
Memories
MOS NOR ROM Layout

Cell (9.5l x 7l)
Programmming using the Active Layer Only
Polysilicon Metal1 Diffusion Metal1 on Diffusion
Memories
MOS NOR ROM Layout

Cell (11l x 7l)
Programmming using the Contact Layer Only
Polysilicon Metal1 Diffusion Metal1 on Diffusion
Memories
MOS NAND ROM

V DD Pull-up devices BL [0] WL [0] BL [1] BL [2] BL [3]
WL [1]
WL [2]
WL [3]
All word lines high by default with exception of selected row

Memories
MOS NAND ROM Layout

Cell (8l x 7l)
Programmming using the Metal-1 Layer Only

No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM
Polysilicon Diffusion Metal1 on Diffusion
Memories
NAND ROM Layout

Cell (5l x 6l)
Programmming using Implants Only
Polysilicon Threshold-altering implant Metal1 on Diffusion Digital Integrated Circuits2nd
Memories
Equivalent Transient Model for MOS NOR ROM

Model for NOR ROM
V DD
BL WL cword rword Cbit
Word line parasitics

Wire capacitance and gate capacitance Wire resistance (polysilicon)
Bit line parasitics

Resistance not dominant (metal) Drain and Gate-Drain capacitance
Memories
Equivalent Transient Model for MOS NAND ROM

V DD
Model for NAND ROM

BL r bit cbit CL
WL cword
r word
Word line parasitics

Similar to NOR ROM
Bit line parasitics

Resistance of cascaded transistors dominates Drain/Source and complete gate capacitance
Memories
Decreasing Word Line Delay

Driver WL Polysilicon word line
Metal word line
(a) Driving the word line from both sides

Metal bypass
WL
K cells
Polysilicon word line
(b) Using a metal bypass (c) Use silicides

Memories
Precharged MOS NOR ROM

f
pre
V DD Precharge devices
WL [0] GND WL [1]
WL [2]
GND WL [3]
BL [0]
BL [1]
BL [2]
BL [3]
PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.
Memories
Non-Volatile Memories The Floating-gate transistor (FAMOS)

Floating gate Gate
Source
tox tox n+ Substrate p
Drain
G S
n+_
Device cross-section
Schematic symbol
Memories
Floating-Gate Transistor Programming

20 V 0V 5V
10 V S
5V
20 V
2 5V S
0V
2 2.5 V S
5V
Avalanche injection
Removing programming voltage leaves charge trapped
Programming results in higher V T .
Memories
A Programmable-Threshold Transistor
Memories
FLOTOX EEPROM
Floating gate Source 2030 nm Gate Drain -10 V 10 V n1 Substrate p 10 nm n1 V GD I
FLOTOX transistor
Fowler-Nordheim I-V characteristic
Memories
EEPROM Cell
BL WL
Absolute threshold control is hard Unprogrammed transistor might be depletion 2 transistor cell
VDD
Memories
Flash EEPROM
Control gate
Floating gate erasure n 1 source
Thin tunneling oxide
programming p- substrate
n 1 drain
Many other options

Memories
Cross-sections of NVM cells
Flash
EPROM
Courtesy Intel
Memories
Basic Operations in a NOR Flash Memory Erase
Memories
Basic Operations in a NOR Flash Memory Write
Memories
Basic Operations in a NOR Flash Memory Read
Memories
NAND Flash Memory

Word line(poly)
Unit Cell
Gate ONO FG
Gate Oxide
Source line (Diff. Layer)
Courtesy Toshiba
Memories
NAND Flash Memory

Select transistor Word lines
Active area
STI
Bit line contact
Source line contact
Courtesy Toshiba
Memories
Characteristics of State-of-the-art NVM
Memories
Read-Write Memories (RAM)

STATIC (SRAM)
Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential
DYNAMIC (DRAM)
Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended
Memories
6-transistor CMOS SRAM Cell

WL V DD
M2
M5 Q M1 BL
M4
Q M6
M3 BL
Memories
CMOS SRAM Analysis (Read)

WL
V DD
BL
Q= 0 M5 V DD M4 Q= 1 V DD M6 V DD BL
M1
Cbit
Cbit
Memories
CMOS SRAM Analysis (Read)

1.2
1
Voltage Rise (V) 0.8 0.6 0.4 0.2 Voltage rise [V] 0 0 0.5 1 1.2 1.5 2 Cell Ratio (CR) 2.5 3
Memories
CMOS SRAM Analysis (Write)

WL V DD M4 M5 Q= 0 Q= 1 M1 V DD M6
BL = 1
BL = 0
Memories
CMOS SRAM Analysis (Write)
Memories
6T-SRAM Layout
VDD
M2 M4
Q
M1 M3
GND
M5 M6
WL
BL
BL
Memories
Resistance-load SRAM Cell

WL V DD
RL M3 BL Q RL Q M4 BL
M1
M2
Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem
Memories
SRAM Characteristics
Memories
3-Transistor DRAM Cell

BL 1 WWL RWL M3 BL 2
WWL
RWL X BL 1 BL 2 V DD V DD 2 V T DV V DD 2 V T
M1
CS
M2
No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V WWL-VTn Digital Integrated Circuits2nd
Memories
3T-DRAM Layout
BL2 BL1 GND
RWL
M3 M2
WWL
M1
Memories
1-Transistor DRAM Cell
Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance
CS D V = VBL V PRE = V BIT V PRE -----------C S + CBL
Voltage swing is small; typically around 250 mV.
Memories
DRAM Cell Observations

1T
DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD
Memories
Sense Amp Operation

V BL
V (1) V PRE
D V (1)
V (0)
Sense amp activated Word line activated
Memories
1-T DRAM Cell

Capacitor
M 1 word line SiO2 Poly
Metal word line
n+
Poly
n+ Inversion layer induced by plate bias
Field Oxide
Diffused bit line Polysilicon gate Polysilicon plate
Cross-section
Layout
Uses Polysilicon-Diffusion Capacitance Expensive in Area

Memories
SEM of poly-diffusion capacitor 1T-DRAM
Memories
Advanced 1T DRAM Cells

Word line Insulating Layer
Cell plate
Capacitor dielectric layer
Cell Plate Si
Capacitor Insulator Storage Node Poly
Refilling Poly
Transfer gate
Isolation Storage electrode
Si Substrate 2nd Field Oxide
Trench Cell
Stacked-capacitor Cell
Memories
Static CAM Memory Cell

Bit Word CAM CAM M6 Word M7 Bit Bit Bit Bit M4 Bit
M8
M9
M5
CAM
CAM
Word Match
S
M3
int
S
M2
M1
Wired-NOR Match Line
Memories
CAM in Cache Memory
CAM
SRAM
ARRAY
ARRAY
Hit Logic
Address Decoder
Input Drivers Sense Amps / Input Drivers
Address
Tag
Hit
R/W
Data
Memories
Periphery
Decoders
Sense Amplifiers Input/Output Buffers Control / Timing Circuitry
Memories
Row Decoders
Collection of 2M complex logic gates Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
Memories
Hierarchical Decoders
Multi-stage implementation improves performance
WL 1
WL 0
A 0A 1 A 0A 1 A 0A 1 A 0A 1
A 2A 3 A 2A 3 A 2A 3 A 2A 3
NAND decoder using 2-input pre-decoders

A1 A0 A0 A1 A3 A2 A2 A3
Memories
Dynamic Decoders
Precharge devices GND GND
VDD WL 3
WL3 WL2 WL1
VDD
VDD
WL 2
V DD WL0
WL 1
WL 0 VDD f A0 A0 A1 A1
A0
A0
A1
A1
2-input NOR decoder
2-input NAND decoder
Memories
4-input pass-transistor based column decoder BL BL BL BL

0 1 2 3
A0
S0 S1
S2
A1 S3
2-input NOR decoder

D
Advantages: speed (tpd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count
Memories
4-to-1 tree based column decoder

BL 0 BL 1 BL 2 BL 3 A0 A0
A1
A1
D
Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches
Memories
Decoder for circular shift-register

V DD WL R V DD
0
V DD WL
1
V DD
V DD WL
2
V DD
V DD
f f
f f R
f f
f f R
f f
f f
Memories
Sense Amplifiers
DV C tp = ---------------Iav large
make D V as small as possible
small
Idea: Use Sense Amplifer
small transition
input
s.a. output
Memories
Differential Sense Amplifier

V DD M3 M4 y Out
bit
M1
M2
bit
SE
M5
Directly applicable to SRAMs

Memories
Differential Sensing SRAM

V DD
PC
V DD
BL EQ WL i
BL y M3 x
V DD M4 M2 M5 2 x x
V DD 2 y 2 x SE
M1 SE
SE SRAM cell i Diff. x Sense 2 x Amp V DD y Output
SE Output (a) SRAM sensing scheme (b) two stage differential amplifier
Memories
Latch-Based Sense Amplifier (DRAM)

EQ BL VDD SE BL
SE
Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point.
Memories
Charge-Redistribution Amplifier
V ref
VL M2 M3 VS C small M1 C large
Transient Response
Concept
Memories
Charge-Redistribution Amplifier V EPROM

DD
SE
M4 Out
Load
V casc
M3
Cout
Cascode device
Ccol
WLC
M2 BL
Column decoder
WL
M1
CBL
EPROM array
Memories
Single-to-Differential Conversion
WL BL Cell x Diff. S.A.
2 x
1 2
V ref
Output
How to make a good Vref?

Memories
Open bitline architecture with dummy cells

EQ L L1 L0 SE
BLL V DD
R0
R1
BLR
SE
CS
CS
CS
CS
CS
CS
Dummy cell
Dummy cell
Memories
DRAM Read Process with Dummy Cell

3 3 2 BL 1 2 BL
V
0 1 t (ns)
BL
V
3
BL
1 t (ns)
reading 0
3 EQ 2 WL
reading 1
SE 1
1 t (ns)
control signals
Memories
Voltage Regulator
VDD
Mdrive VDL
VREF Vbias
Equivalent Model
VREF
Mdrive
VDL
Memories
Charge Pump
Memories
DRAM Timing
Memories
RDRAM Architecture
Bus Clocks Data bus k k3 l memory array
network mux/demux
Column demux Row packet dec. packet dec.
demux
Memories
Address Transition Detection

V DD DELAY td DELAY td DELAY td
A0
ATD
ATD
A1
A N2 1
Memories
Reliability and Yield
Memories
Sensing Parameters in DRAM

1000
V smax (mv)
C D (1F)
smax V , DD V ,S 10 C ,S Q ,D C
100
C S (1F)
Q S (1C)
V DD (V)
Q S 5 C S V DD / 2 V smax 5 Q S / ( C S 1 C D )
4K
64K
1M 16M 256M 4G
/ chip)
64G
Memory Capacity (bits Digital Integrated Circuits2nd
From [Itoh01]
Memories
Noise Sources in 1T DRam

BL CWBL WL leakage CS substrate Adjacent BL
a -particles
electrode
Ccross
Memories
Open Bit-line Architecture Cross Coupling
EQ
WL 1 BL C BL C
WL 0
WL C WBL D Sense Amplifier
C WBL
WL D
WL 0
WL 1
BL C BL
Memories
Folded-Bitline Architecture
WL 1
BL
WL 1
WL 0 C
WBL
WL 0
WL D
WL D x
CBL C CBL
CWBL
Sense EQ Amplifier x
BL
Memories
Transposed-Bitline Architecture
Ccross BL 9 BL BL BL 99 (a) Straightforward bit-line routing Ccross BL 9 BL BL BL 99
(b) Transposed bit-line architecture
SA
SA
Memories
Alpha-particles (or Neutrons)

a -particle WL BL n1
1
1 1 1 1 1 2 2 2 2 2
V DD SiO 2
1 Particle ~ 1 Million Carriers

Memories
Yield
Yield curves at different stages of process maturity (from [Veendrick92])
Memories
Redundancy
Redundant rows Redundant columns Memory Array Row Address : Fuse Bank
Row Decoder
Column Decoder Column Address
Memories
Error-Correcting Codes
Example: Hamming Codes
e.g. B3 Wrong
with
1 1 =3
Memories
Redundancy and Error Correction
Memories
Sources of Power Dissipation in Memories

V DD CHIP nC DE V INT f C PT V INT f I DCP selected I DD 5 S C iD V if1S I DCP m mi act
n m(n 2 1)i hld non-selected ARRAY
ROW DEC PERIPHERY
mC DE V INT f COLUMN DEC

V SS
From [Itoh00]
Memories
Data Retention in SRAM

1.30u 1.10u 0.13 m m CMOS 900n
Ileakage
700n 500n
Factor 7
0.18 m m CMOS
(A) 300n
100n
0.00 .600 1.20
1.80
VDD
SRAM leakage increases with technology scaling

Memories
Suppressing Leakage in SRAM

V DD low-threshold transistor V DD sleep V DD,int SRAM cell SRAM cell SRAM cell V DDL
sleep
V DD,int
SRAM cell
SRAM cell
SRAM cell
sleep
V SS,int
Inserting Extra Resistance

Reducing the supply voltage

Memories
Data Retention in DRAM
From [Itoh00]
Memories
Case Studies
Programmable
Logic Array
SRAM
Flash
Memory
Memories
PLA versus ROM

Programmable Logic Array
structured approach to random logic two level logic implementation NOR-NOR (product of sums) NAND-NAND (sum of products)
IDENTICAL TO ROM!
Main difference
ROM: fully populated PLA: one element per minterm Note: Importance of PLAs has drastically reduced 1. slow 2. better software techniques (mutli-level logic synthesis)
But
Memories
Programmable Logic Array

Pseudo-NMOS PLA
GND GND GND GND V DD GND
GND
GND
V DD
X0
X0
X1
X1
X2
X2
f0
f1
AND-plane
OR-plane
Memories
Dynamic PLA
f AND GND V DD f
OR
f f AND V DD
OR
X0
X0
X1
X1
X2
X2
f0
f 1 GND
AND-plane
OR-plane
Memories
Clock Signal Generation for self-timed dynamic PLA

f f f Dummy AND row
AND
AND
tpre teval f
OR
AND
Dummy AND row
OR
(a) Clock signals
(b) Timing generation circuitry
Memories
PLA Layout
VDD And-Plane Or-Plane f GND
x0 x0 x1 x1 x2 x2 Pull-up devices
f0 f1 Pull-up devices
Memories
4 Mbit SRAM Hierarchical Word-line Architecture
Memories
Bit-line Circuitry
Bit-line load Block select ATD
BEQ Local WL Memory cell B /T CD CD I/O line I /O Sense amplifier B /T CD I /O
Memories
Sense Amplifier (and Waveforms)

Address
I /O SEQ BS I /O
ATD
Block select ATD
BEQ
SA
BS
SA SEQ SEQ SEQ SEQ DATA Dei
Vdd I/O Lines GND

SEQ Vdd SA, SA GND
DATA
BS
Data-cut
Memories
1 Gbit Flash Memory
From [Nakamura02]
Memories
Writing Flash Memory
108 106
104
102 100 0V 1V 2V 3V 4V
Read
Number of cells Vt of memory cells Evolution of thresholds
Final Distribution
From [Nakamura02]
Memories
2 125mm
1Gbit NAND Flash Memory

32 word lines x 1024 blocks
Charge pump 2kB Page buffer & cache
10.7mm
16896 bit lines
11.7mm
From [Nakamura02]
Memories
125mm2 1Gbit NAND Flash Memory

0.13m p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al Cell size 0.077m2 Chip size 125.2mm2 Organization 2112 x 8b x 64 page x 1k block Power supply 2.7V-3.6V Cycle time 50ns Read time 25s Program time 200s / page Erase time 2ms / block Technology
From [Nakamura02]
Memories
Semiconductor Memory Trends (up to the 90s)
Memory Size as a function of time: x 4 every three years

Memories
Semiconductor Memory Trends (updated)
From [Itoh01]
Memories
Trends in Memory Cell Area
From [Itoh01]
Memories
Semiconductor Memory Trends
Technology feature size for different SRAM generations

Memories

Chapter 12

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Digital Integrated Circuits

Semiconductor Memory Classification

Non-Random Access FIFO LIFO Shift Register CAM

Digital Integrated Circuits2nd

Memory Timing: Definitions

Digital Integrated Circuits2nd

Memory Architecture: Decoders

Input-Output ( M bits) Decoder reduces the number of select signals

Digital Integrated Circuits2nd

Array-Structured Memory Architecture

Amplify swing to rail-to-rail amplitude

Selects appropriate word

Digital Integrated Circuits2nd

Hierarchical Memory Architecture

Block Diagram of 4 Mbit SRAM

Sense amplifier and write driver

Local row deco

Digital Integrated Circuits2nd

Data (64 bits)

I/O Buffers I/O Buffers

Control Logic R/W Address (9 bits)

CAM Array 2 words 3 64 bits

Digital Integrated Circuits2nd

Memory Timing: Approaches

DRAM Timing Multiplexed Adressing

SRAM Timing Self-timed

Digital Integrated Circuits2nd

Read-Only Memory Cells

Digital Integrated Circuits2nd

V bias Pull-down loads

Digital Integrated Circuits2nd

MOS NOR ROM

WL [2] GND WL [3]

Digital Integrated Circuits2nd

MOS NOR ROM Layout

Programmming using the Active Layer Only

Polysilicon Metal1 Diffusion Metal1 on Diffusion

Digital Integrated Circuits2nd

MOS NOR ROM Layout

Programmming using the Contact Layer Only

Polysilicon Metal1 Diffusion Metal1 on Diffusion

Digital Integrated Circuits2nd

MOS NAND ROM

All word lines high by default with exception of selected row

MOS NAND ROM Layout

Programmming using the Metal-1 Layer Only

Polysilicon Diffusion Metal1 on Diffusion

Digital Integrated Circuits2nd

NAND ROM Layout

Programmming using Implants Only

Polysilicon Threshold-altering implant Metal1 on Diffusion Digital Integrated Circuits2nd

Equivalent Transient Model for MOS NOR ROM

BL WL cword rword Cbit

Word line parasitics

Bit line parasitics

Digital Integrated Circuits2nd

Equivalent Transient Model for MOS NAND ROM

Model for NAND ROM

Word line parasitics

Bit line parasitics

Digital Integrated Circuits2nd

Decreasing Word Line Delay

Metal word line

(a) Driving the word line from both sides