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Dr. Gheith Abandah [Adapted from the slides of Professor Mary Irwin (www.cse.psu.edu/~mji) which in turn Adapted from Computer Organization and Design, Patterson & Hennessy, 2005, UCB]
Control needs to
1.
Memory
2.
issue signals to control the information flow between the Datapath components and to control what operations they perform
control instruction sequencing
Fetch
3.
Exec
Decode
components the functional units and storage (e.g., register file) needed to execute instructions interconnects - components connected so that the instructions can be accomplished and so that data can be loaded from and stored to Memory
2
For a given level of function, however, that system is best in which one can specify things with the most simplicity and straightforwardness. Simplicity and straightforwardness proceed from conceptual integrity. Ease of use, then, dictates unity of design, conceptual integrity. The Mythical Man-Month, Brooks, pg 44
RISC philosophy
fixed instruction lengths load-store instruction sets limited addressing modes limited operations
MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC, HP (Compaq) Alpha, Instruction sets are measured by how well compilers use them as opposed to how well assembly language programmers use them Design goals: speed, cost (design, fabrication, test, packaging), size, power consumption, reliability, memory space (embedded systems)
Instruction Categories
Registers R0 - R31
PC HI
LO
OP
OP OP
CPE 232 MIPS ISA
rs
rs
rt
rd
sa
funct
R format
rt
immediate
I format
J format
5
jump target
Binary
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 11100 11101 11110 11111
Decimal
0 1 2 3 4 5 6 7 8 9 232 - 4 232 - 3 232 - 2 232 - 1
6
... ...
23 22 21 3 2 1
20 0
1 1 1
...
1 1 1 1
bit
1 0 0 0
...
0 0 0 0
232 - 1
American Std Code for Info Interchange (ASCII): 8-bit bytes representing characters
Char ASCII Char ASCII Char ASCII Char ASCII Char ASCII Char
ASCII
0
1 2 3 4 5 6 7 8 9 10 11 12 15
Null
32
33 34 35
space
! # $ % & ( ) * + , /
48
49 50 51 52 53 54 55 56 57 58 59 60 63
0
1 2 3 4 5 6 7 8 9 : ; < ?
64
65 66 67 68 69 70 71 72 73 74 75 76 79
@
A B C D E F G H I J K L O
96
97 98 99 100 101 102 103 104 105 106 107 108 111
`
a b c d e f g h i j k l o
112
113 114 115 116 117 118 119 120 121 122 123 124 127
p
q r s t u v w x y z { | DEL
36 37 38 39 40 41 42 43 44 47
MIPS assembly language arithmetic statement add sub $t0, $s1, $s2 $t0, $s1, $s2
Each arithmetic instruction performs only one operation Each arithmetic instruction fits in 32 bits and specifies exactly three operands
destination source1 op source2
Operand order is fixed (destination first) Those operands are all contained in the datapaths register file ($t0,$s1,$s2) indicated by $
8
Name
Preserve on call? constant 0 (hardware) n.a. reserved for assembler n.a. returned values no arguments yes temporaries no saved values yes temporaries no global pointer yes stack pointer yes frame pointer yes return addr (hardware) yes
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Usage
Register File
32 bits 5 5 5 32 32 locations 32 src2 32 src1
src1 addr
src2 addr dst addr write data
data
Registers are
data
- But register files with more locations write control are slower (e.g., a 64 word file could be as much as 50% slower than a 32 word file) - Read/write port increase impacts speed quadratically
10
Instructions, like registers and words of data, are 32 bits long Arithmetic Instruction Format (R format):
op rs rt rd
opcode that specifies the operation register file address of the first source operand register file address of the second source operand register file address of the results destination shift amount (for shift instructions)
shamt 5-bits
funct
CPE 232 MIPS ISA
6-bits
MIPS has two basic data transfer instructions for accessing memory
lw
sw
$t0, 4($s3)
$t0, 8($s3)
The data is loaded into (lw) or stored from (sw) a register in the register file a 5 bit address The memory address a 32 bit address is formed by adding the contents of the base address register to the offset value
A 16-bit field meaning access is limited to memory locations within a region of 213 or 8,192 words (215 or 32,768 bytes) of the address in the base register Note that the offset can be positive or negative
12
2410 + $s2 =
$t0 $s2
data
CPE 232 MIPS ISA
Byte Addresses
Since 8-bit bytes are so useful, most architectures address individual bytes in memory
14
MIPS provides special instructions to move bytes lb sb $t0, 1($s3) $t0, 6($s3)
op rs rt
memory
load byte places the byte from memory in the rightmost 8 bits of the destination register
- what happens to the other bits in the register?
store byte takes the byte from the rightmost 8 bits of a register and writes it to a byte in memory
- what happens to the other bits in the memory word?
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Ex:
if (i==j) h = i + j;
bne $s0, $s1, Lbl1 add $s3, $s0, $s1 ...
Lbl1:
limits the branch distance to -215 to +215-1 instructions from the (instruction after the) branch instruction, but most branches are local anyway
from the low order 16 bits of the branch instruction
16
offset
sign-extend
00 32 32 Add 32 4 Add
PC
32
CPE 232 MIPS ISA
32
32
?
17
We have beq, bne, but what about other kinds of brances (e.g., branch-if-less-than)? For this, we need yet another instruction, slt Set on less than instruction:
slt $t0, $s0, $s1 # if $s0 < $s1 # $t0 = 1 # $t0 = 0 then else
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Can use slt, beq, bne, and the fixed value of 0 in register $zero to create other conditions
blt $s1, $s2, Label $at, $s1, $s2 $at, $zero, Label #$at set to 1 if # $s1 < $s2
ble $s1, $s2, Label bgt $s1, $s2, Label bge $s1, $s2, Label
Such branches are included in the instruction set as pseudo instructions - recognized (and expanded) by the assembler
00 32
PC
CPE 232 MIPS ISA
32
20
What if the branch destination is further away than can be captured in 16 bits?
The assembler comes to the rescue it inserts an unconditional jump to the branch target and inverts the condition beq $s0, $s1, L1
becomes
bne j
L2:
$s0, $s1, L2 L1
21
Saves PC+4 in register $ra to have a link to the next instruction for the procedure return Machine format (J format):
op 26 bit address
What if the callee needs more registers? What if the procedure is recursive?
uses a stack a last-in-first-out queue in memory for passing additional values or saving (recursive) return address(es)
high addr
One of the general registers, $sp, is used to address the stack (which grows from high address to low address)
top of stack
$sp
remove data from the stack pop data from stack at $sp $sp = $sp + 4
23
low addr
put typical constants in memory and load them create hard-wired registers (like $zero) for constants like 1 have special instructions that contain constants !
I format
We'd also like to be able to load a 32 bit constant into a register, for this we must use two instructions
a new "load upper immediate" instruction
Then must get the lower order bits right, use ori $t0, $t0, 1010101010101010
1010101010101010 0000000000000000 1010101010101010 0000000000000000 1010101010101010 1010101010101010
25
Memory
11100
src2 32 data
read/write addr
32
230 words
read data
32 32
PC
write data
32 32 4 0 5 1 6 2 7 3
Decode
26
0 and 32 add $s1, $s2, $s3 0 and 34 sub $s1, $s2, $s3 8 addi $s1, $s2, 6
or immediate
load word store word load byte store byte load upper imm Cond. Branch (I & R format) br on equal br on not equal
13
35 43 32 40 15 4 5
$s1 = $s2 v 6
$s1 = Memory($s2+24) Memory($s2+24) = $s1 $s1 = Memory($s2+25) Memory($s2+25) = $s1 $s1 = 6 * 216 if ($s1==$s2) go to L if ($s1 !=$s2) go to L
0 and 42 slt
10 2 0 and 8 3
op
Register
word operand
Base (displacement) addressing operand is at the memory location whose address is the sum of a register and a 16-bit constant contained within the instruction
rs rt offset
op
Memory
word or byte operand
base register
0($a0) addr($zero)
op
CPE 232 MIPS ISA
PC-relative addressing instruction address is the sum of the PC and a 16-bit constant contained within the instruction
rs rt offset
op
Memory
branch destination instruction
Pseudo-direct addressing instruction address is the 26bit constant contained within the instruction concatenated with the upper 4 bits of the PC
jump address
op
Memory
|| jump destination instruction
29
fixed size instructions 32-bits small number of instruction formats opcode always the first 6 bits
Smaller is faster
limited instruction set limited number of registers in register file limited number of addressing modes
arithmetic operands from the register file (load-store machine) allow instructions to contain immediate operands
30