Advanced Microprocessors & Microcontrollers / UNIT VI / Microcontroller 8051 Electronics & Telecommunication Engineering Department

Syllabus of Unit VI
8051 instruction set, Interrupts, Programming exercises for interfaced with keyboard, LED Matrix, serial communication

Learning Objectives:
By the end of this unit, the students will be able to :
Understand the syntax & operation of various instructions of 8051 microcontroller Get an in-depth knowledge about interrupts of c 8051 Understand the details about interfacing of various peripherals like keyboard and LED matrix Acquire knowledge about how serial communication takes place in c 8051

The 8051 instruction set

Different types of instructions included in the instruction set are :
Data Transfer instructions Stack related instructions Arithmetic instructions Logical Instructions Branching Instructions Bit Manipulation instructions

Data Transfer instructions

MOV D,S -Transfer data from 8-bit source to 8-bit destination -Source :register (A,B,R0-R7)/ memory/ data -Destination :register/memory -Eg: MOV A,#55H MOV R0, A MOV @R1,#55H MOVX D,S -X --Data move external to c 8051 -All external data moves must involve register A -R0, R1 & DPTR hold address of data byte in external RAM -Eg: MOVX A, @DPTR MOVX @R1,A
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Data Transfer instructions

MOVC A,Source
-C highlights use of op-codes for moving data from source address in code ROM to register A -Address calculation : A+PC / DPTR -Eg: MOVC A @A+DPTR MOVC A ,@A+PC

XCH A, Source
Exchange data between register A & internal RAM source Eg: XCH A,R7 XCH A,@R1
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Data Transfer instructions

XCHD A, Source Exchange Lower nibble between register A & internal RAM source Eg: XCHD A,@R1

Stack related instructions

Upon RESET , SP register (8-bit) points to 07H
PUSH Source - Copy data from source address to stack memory at address SP = SP + 1 Eg: PUSH 00H POP Destination -Copy byte from (internal RAM) stack to internal RAM destination - After POP, SP = SP-1 Eg: POP 01H

Arithmetic instructions
INC Destination
-increment destination by 1 -Destination : 8/16 bit register / memory -Eg: INC A INC @R1 INC DPTR

DEC Destination
decrement destination by 1 - Destination : 8-bit register / memory -Eg: DEC A DEC @R0 Note: DPTR can only be incremented and cant 8 be decremented

Arithmetic instructions
ADD / ADDC D,S
-Add source to destination without / with carry -CF, AC & OV flag affected - Register A:-Destination; Source:- data/reg/memory -Eg: ADD A,R5 ADDC A,@R1 ADD A,#56H

SUBB D,S
Subtract source from destination with borrow -CF, AC & OV flag affected - Register A:-Destination; Source:- data/reg/memory 9 -Eg: SUBB A,R5 SUBB A,@R0 SUBB A,#99H

Arithmetic instructions
MUL AB
-Multiply contents of register A & B -CF =0, & OV flag affected according to result - Result : 16 bit copied in register B(MSB) & A(LSB)

DIV AB
-Divide contents of register A by contents of register B -CF =0, & OV flag affected according to result - Result : 16 bit copied in register B(remainder) & A(Quotient)
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Arithmetic instructions
DA A
-Decimal adjust register A -Used for BCD number addition - Used after ADD / ADDC instructions - CF & AC flag affected according to result

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Logical instructions
ANL D,S
-Performs logical ANDing of destination & source -Destination : A/memory; Source:data/register/memory - Eg: ANL A,#0FH ANL A,R5 ANL 10H,A

ORL D,S

-Performs logical ORing of destination & source

-Destination : A/memory; Source:data/register/memory - Eg: ORL A,#28H ORL A,@R0 ORL 10H,#23H
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Logical instructions
XRL D,S
-Performs logical X-ORing of destination & source -Destination : A/memory; Source:data/register/memory - Eg: XRL A,#0FH ANL A,R5 XRL A,@R1

CPL A

-Compliment accumulator
-gives 1s compliment of accumulator data SWAP A 13 -Exchange the upper & lower nibbles of accumulator

Logical instructions
RL A -Rotate data of accumulator towards left without
carry

RLC A - Rotate data of accumulator towards left with carry RR A -Rotate data of accumulator towards right without
carry

RRC A - Rotate data of accumulator towards right with

carry
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Branching instructions
Program branching instructions are used to control the flow of actions in a program Some instructions provide decision making capabilities and transfer control to other parts of the program. e.g. conditional and unconditional branches

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Branching instructions
The 8051 provides 2 forms for the CALL instruction:

Absolute Call ACALL

Uses an 11-bit address The subroutine must be within the same 2K page.

Long Call LCALL

Uses a 16-bit address The subroutine can be anywhere. Both forms push the 16-bit address of PC on the stack and update the stack pointer. 16

Branching instructions
The 8051 provides 2 forms for the return instruction:

Return from subroutine RET

Pop the return address from the stack and continue execution there.

Return from ISR RETI

Pop the return address from the stack. Restore the interrupt logic to accept additional interrupts at the same priority level as the one just processed. Continue execution at the address retrieved from the stack. 17 The PSW is not automatically restored.

Branching instructions
The 8051 provides four different types of unconditional jump instructions:

Short Jump SJMP addr

Uses an 8-bit signed offset relative to the 1st byte of the next instruction. the range of destination allowed is from -128 Long to+127 bytes from the instruction

Long Jump LJMP addr

Uses a 16-bit address. 3 byte instruction capable of referencing any location in the entire 64K of program memory.
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Branching instructions
Absolute Jump AJMP
Uses an 11-bit address substituted for the lower 11 bits of the PC to calculate the 16-bit address of the target.. 2 byte instruction The location referenced must be within 2K Bytes

Indirect Jump
8-bit unsigned value of the acc added to the 16-bit data pointer and resulting sum is returned to the PC Neither ACC nor DPTR is altered No flags are affected 19 JMP @A + DPTR

Branching instructions
The 8051 supports different conditional jump instructions. ALL conditional jump instructions use an 8-bit address.

JZ / JNZ label :
Jump if the A == 0 / A != 0

JC / JNC label :
Jump if the Carry flag is set / cleared.

DJNZ destination, label :

Decrement destination data & Jump if not zero
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Branching instructions
JB bit, Target:
Jump to target location if the specified bit = 1 For eg: JB P1.3,L1

JNB bit, Target:

Jump to target location if the bit value = 0 For eg: JB P3.3,L1

JBC bit, Target:

Jump if the specified bit is set. Then clear the bit. For eg: JBC P2.5,L1
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Branching instructions
CJNE destination, source, relative address
Compare and Jump if Not Equal Destination : accumulator /any one of the Rn registers Source: register / memory / immediate data Only CF affected For Eg: CJNE A,#99H,L1 CJNE A,@R0,next CJNE R5,#87H,L2
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Bit Manipulation instructions

This group of instructions is associated with the single-bit operations of the 8051. This group allows manipulating the individual bits of bit addressable registers and memory locations as well as the CY flag. The P, OV, and AC flags cannot be directly altered. This group includes: Set, clear, and, or complement, move. Conditional jumps.
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Bit Manipulation instructions

CLR C :- Clear the Carry flag CLR Bit :- Clear the bit i.e bit value=0
For eg: CLR 67H

SETB C :- Set the Carry flag SETB bit :- Set the specified bit
For eg: SETB PSW.4

CPL C :- Compliment the carry flag CPL bit :- Compliment the bit value
For eg: CPL P2.2
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Bit Manipulation instructions

MOV C,bit :- Copy value of bit to carry flag
For eg: MOV C,P2.3 MOV bit,C :- Copy value of carry flag to given bit For eg: MOV P2.3,C ANL C,bit :- AND bit to carry flag For eg: ANL C,P3.3 ANL C,/bit :- AND complimented value of bit to carry flag For eg: ANL C,/P3.3

ORL C,bit :- OR bit to carry flag

For eg: ORL C,P3.3 ORL C,/bit :- OR complimented value of bit to carry flag 25 For eg: ORL C,/P3.3

Interrupts Programming
An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service. Interrupts vs. Polling A single microcontroller can serve several devices. There are two ways to do that: interrupts polling. The program which is associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler.

Steps in executing an interrupt

Finish current instruction and saves the PC on stack.
Jumps to a fixed location in memory depend on type of interrupt Starts to execute the interrupt service routine until RETI (return from interrupt) Upon executing the RETI the microcontroller returns to the place where it was interrupted. Get pop PC from stack

Interrupt Sources
Original 8051 has 6 sources of interrupts
Reset Timer 0 overflow Timer 1 overflow External Interrupt 0 External Interrupt 1 Serial Port events (buffer full, buffer empty, etc)

Interrupt Vectors
Each interrupt has a specific place in code memory where program execution (interrupt service routine) begins.
RESET : 0000H External Interrupt 0 : 0003h Timer 0 overflow : 000Bh External Interrupt 1 : 0013h Timer 1 overflow : 001Bh Serial : 0023h

Interrupt Enable (IE) register

All interrupt are disabled after reset We can enable and disable them bye IE

Enabling and disabling an interrupt

by bit operation Recommended in the middle of program SETB EA / IE.7 ;Enable All SETB ET0 /IE.1 ;Enable Timer0 ovrf SETB ET1/ IE.3 ;Enable Timer1 ovrf SETB EX0 / IE.0 ;Enable INT0 SETB EX1 / IE.2 ;Enable INT1 SETB ES / IE.4 ;Enable Serial port by mov instruction Recommended in the first of program MOV IE, #10010110B

Timer ISR
Notice that There is no need for a CLR TFx instruction in timer ISR 8051 clears the TF internally upon jumping to ISR Notice that We must reload timer in mode 1 There is no need on mode 2 (timer auto reload) (MSB) TF1 TR1 Timer 1 TF0 TR0 Timer0 IE1 IT1 IE0 for Interrupt (LSB) IT0

External interrupt type control

By low nibble of Timer control register TCON IE0 (IE1): External interrupt 0(1) edge flag. set by CPU when external interrupt edge (H-to-L) is detected. Does not affected by H-to-L while ISR is executed(no int on int) Cleared by CPU when RETI executed. does not latch low-level triggered interrupt

IT0 (IT1): interrupt 0 (1) type control bit.

Set/cleared by software IT=1 / 0 edge / low level trigger

Interrupt Priorities
All interrupts have a power on default priority order. 1. Reset

2. External interrupt 0 (INT0)

3. Timer interrupt0 (TF0) 4. External interrupt 1 (INT1) 5. Timer interrupt1 (TF1) 6. Serial communication (RI+TI)

The interrupt with the highest PRIORITY gets serviced first.

Priority can also be set to high or low by IP reg.

Interrupt Priorities (IP) Register

PT2 PS PT1 PX1 PT0 PX0 IP.7 & IP.6 : reserved IP.5: timer 2 interrupt priority bit(8052 only) IP.4: serial port interrupt priority bit IP.3: timer 1 interrupt priority bit IP.2: external interrupt 1 priority bit IP.1: timer 0 interrupt priority bit IP.0: external interrupt 0 priority bit Priority order decided by putting 1 in a particular IP bit In case of multiple logic 1s priority is resolved using default priority scheme
-----

Interrupt inside an interrupt

A high-priority interrupt can interrupt a lowpriority interrupt All interrupt are latched internally Low-priority interrupt wait until 8051 has finished servicing the high-priority interrupt

Interfacing of Matrix Keyboard with 8051

Keyboards , LCDs most widely used input/output devices of the 8051 Contents to be covered:
keyboard fundamentals key press and key detection mechanisms Details of keyboard interfacing to 8051.

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Interfacing the Keyboard with 8051

Keyboards organized in a matrix of rows and columns. The CPU accesses both rows and column through ports When a key pressed, a row and column make a connect; otherwise, there is no connection between row and column. Microcontroller scans the keys continuously to identify which one has been activated

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Keyboard interfacing with 8051

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Key closure detection

Key not pressed
C1

1
P2.0
R1

Key pressed
C1

1
P2.4
8051

P2.0

R1

P2.4
8051

LED Interfacing with 8051

most widely used means of taking output. Find application as indicators during experimentations to check the validity of results at different stages. very cheap and easily available in a variety of shape, size and colors. LEDs need approximately 10mA current to flow through them in order to glow at maximum intensity Logic 1=LED switched off Logic 0 =LED will glow at full intensity.
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LED Interfacing with 8051

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Serial Communication using 8051

Basics of serial communication

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Basics of serial communication

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Basics of serial communication

Start and stop bits

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Basics of serial communication

RS232 pins

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Basics of serial communication

Data communication classification

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Serial Communication using 8051

RxD and TxD pins in the 8051
TxD pin 11 of the 8051 (P3.1) RxD pin 10 of the 8051 (P3.0)

Pins are TTL compatible A line driver is hence necessary to make them RS232 compatible Two such line drivers are:
MAX 232 MAX 233
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Serial Communication using 8051

MAX232

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Serial Communication using 8051

MAX 233

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8051 SERIAL COMMUNICATION PROGRAMMING

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8051 SERIAL COMMUNICATION PROGRAMMING

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8051 Registers for serial communication

SBUF
Serial buffer register 8 bit

SCON
Serial Control register 8 bit

PCON
Power control register -8 bit
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8051 Registers for serial communication

SCON (Serial control) register format

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SCON register- Details

SM0 and SM1 are D7 and D6 of the SCON
SM0 0 0 1 1 SM1 0 Serial Mode 0 1 Serial Mode 1,8 bit data, 1 stop bit, 1 start bit 0 Serial Mode 2 1 Serial Mode 3

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Doubling the baud rate in the 8051

To use a higher frequency crystal To change a bit in the PCON register PCON (Power Control ) Byte Addressable 8 bit register

D7 SMOD

--

--

--

GF1 GF0

D0 PD IDL

SMOD =1 ; Baud Rate doubled GF1-GF0 : General purpose Flag Bits PD- Power Down Mode IDL Idle Mode

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Baud rates for SMOD=1

Machine cycle freq. = 11.0592 MHz / 12 = 921.6 kHz 921.6 kHz / 16 = 57,600 Hz since SMOD = 1

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The power down & Idle modes

To save power of battery operated devices, 8051 can be used in
Idle mode (IDL = 1) Power down mode (PD = 1)

Clock Gen.

Interrupt, Serial Port, Timers

CPU
PD IDL
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Summary :
The instruction set of 8051 consists of simple instructions almost similar to that of p 8085 8051 consists of 6 interrupts ( 3 internal, 2 external & 1 RESET interrupt) IE, IP registers used for interrupts 4*4 matrix keyboard & LEDs can be interfaced with 8051 using simple routines 8051 consists of 1 serial port which performs fullduplex asynchronous transmission & reception of information SBUF, SCON & PCON registers are used for serial communication 59

References :
The 8051 Microcontroller Architecture, programming & Applications by Kenneth J. Ayala The 8051 Microcontroller & Embedded Systems
by Muhammad Ali Mazidi &Janice Gillispie Mazidi

8051 Microcontroller Hardware, software & Applications by V.Udayshankara & M. S.

Mallikajunaswamy

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