DDR3 CONTROLLER DESIGN

Pavan Kumar Reddy Brindha AG Vaishnavi S Lekshmi Vishwanath Amritha Krishna R S Anju C Arun Rajan (621638) (621685) (621703) (621653) (621663) (621661) (621844)

OVERVIEW
INTRODUCTION OBJECTIVE MOTIVATION ARCHITECTURE OF DDR3 CONTROLLER MICRO ARCHITECTURE OF DDR3 CONTROLLER TASKS COMPLETED

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DDR3 CONTROLLER DESIGN

INTRODUCTION
DRAM (Dynamic random access memory) Random access : indicates that any position in the memory can be accessed by providing the row and column address

Dynamic : The memory is designed using transistor and capacitor. This involves periodic charging of the capacitors

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DDR3 CONTROLLER DESIGN

INTRODUCTION CONT

Specific features of DDR3 1) Faster than earlier generations as it provides data in both edges of the clock cycle 2) Better performance than previous generation DDR2 by writing /reading 8 consecutive locations. DDR2 can read/write 4 consecutive locations 3) Lower power due to smaller die-size and lower supply voltage

4) Larger densities. Reduces the number of pins by using row and column multiplexing

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DDR3 CONTROLLER DESIGN

OBJECTIVE
To design a DDR3 memory controller for interfacing AXI and DDR3 DRAM memory

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DDR3 CONTROLLER DESIGN

MOTIVATION
DDR3 memory controller acts as an interface between AXI and DDR3 DRAM memory Row, column and bank address decoding is done by this module

Takes care of write and read latencies

Interprets the commands issued by the AXI and translates it to DDR3 memory Takes care of periodic refresh of memory

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DDR3 CONTROLLER DESIGN

ARCHITECTURE OF DDR3 CONTROLLER

DDR3_CKE CLK

RESET_N

INITIALISATION (VENDOR SPECIFIC)

DDR3_CS

REFRESH TIMER

DDR3_CK_N DDR3_CK

DDR3_CAS_N

DEVICE READY LOGIC

ADDR RD WR WDATA CMD_ACK DEV_RDY

COMMAND CONTROLLER

COMMAND PATH

DDR3_RAS_N DDR3_ADDR DDR3_BA

ADDRESS DECODER

DDR3_ODT DDR3_DM DDR3_WE_N

ROW STATUS LOGIC

PREV ROW ADDR STATUS PREV ROW ADDR STATUS PREV ROW ADDR STATUS PREV ROW ADDR STATUS

DDR3_DQ

WRITE PATH
DDR3_DQS

READ PATH
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MICRO ARCHITECTURE OF DDR3 CONTROLLER

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DDR3 CONTROLLER DESIGN

RAS_N CS

WE_N CAS_N

RST_N

WRITE

READ

CLK

RST_N

CK CK_N CLK RST_N DLL_RESET DLL_ENABLE BA[2:0] MRS ODT CKE ZQCL

CLK PRECHAR REFRESH ACTIVE

mrs[18:16]
mrs[15:0]

ADDR_OUT[15:0] BA_ADDR[2:0] CS RAS_N

INITIALISATION MODULE

MRS MODULE

COMMAND PATH MODULE

BA_ADDR[2:0]

DEV_READY

MRS RST_N NOP CLK

CAS_N
CA[{11,9:0}] WE_N RA[15:0]

CLK

WRITE COMMAND_ACK
REFRESH ACTIVE

OPENED_ROW

RST_N

AXI

READ

FSM MODULE
PRECHARGE

MATCH

ADDRESS DECODER MODULE

DATA[31:0] AXI SLAVE CONTROLLER DEV_READY

DQS DQS_N DQ[7:0]

WRITE PATH MODULE

WRITE WRITE(AXI) READ CLK RST_N

AXI SLAVE CONTROLLER

ADDR[31:0]

DQS

DATA_VALID

AXI SLAVE CONTROLLER

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READ_DATA[31:0]

READ PATH MODULE

DQS_N DQ[7:0] 9

DDR3 CONTROLLER DESIGN

INITIALIZATION
Purpose For creating source synchronization (ie for creating the clock for memory) To inform the timing setup (in terms of latencies) to the memory Provides On Die Termination(ODT) information for fabrication Provides the calibration precision required for DDR-PHY

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INITILIZATION
IDLE WAIT 500s WAIT TXPR LOAD MODE COMMAND TO MR2 WAIT TMRD LOAD MODE COMMAND TO MR1 LOAD MODE COMMAND TO MR0

CONT

LOAD MODE COMMAND TO MR3

WAIT TMOD ZQCL CALIBRATION

WAIT ZQCL

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INITIALIZATION DONE DDR3 CONTROLLER DESIGN

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INITILIZATION
Mode register select

CONT

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INITILIZATION
Device ready

CONT

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INITILIZATION

CONT

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INITILIZATION
CHALLENGES Specification mismatch ZQCL mismatch Timing violations tCK(avg ) parameter violation

CONT
SOLUTIONS

Changed the clock-period and parameters accordingly Added ZQCL command to command path The code was debugged and added timing delays The column latency and additive latency were changed accordingly

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ADDRESS DECODER
Purpose Addressing of 8GB memory Column address Row address Bank Address Maintains row status logic Organization 8 banks with 1GB each This addressed as 4GB address at a time A11 bit of column address is used to select top 4GB or bottom 4GB 16 bit row address 10 bit column address
512 512
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A11

DDR3 CONTROLLER DESIGN

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ADDRESS DECODER CONT

CHALLENGES Row open status Auto - precharge and burst chop SOLUTIONS OPEN signal was generated along with MATCH signal Auto-precharge Burst chop Burst size Burst type : ignored :0 :4 : sequential

Address - one clock cycle

Temporary register was used to capture the address

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COMMAND PATH
Purpose Helps in decoding the command issued by the AXI and indicates it to the memory by the ras_n, cas_n, we_n and cs_n signals Based on the command, command path either passes MRS contents or the row /column address to the addr_out Achieves address multiplexing by passing row address during activate/precharge commands The column address is passed during read and write commands Based on the command, command path either passes register address or bank address through the ba_out

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COMMAND PATH CONT

MRS
0

addr out

ADDRESS DECODER

!MRS/OC

MRS
0

ba ADDRESS DECODER
nop active precharge read write refresh
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1 !MRS/OC

COMMAND DECODING LOGIC

cas_n ras_n cs_n we_n

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DDR3 CONTROLLER DESIGN

COMMAND PATH CONT

MODE REGISTER SET
Purpose Used to provide the setup information to memory in terms of four registers. Provides the following information to the memory Column write latency Additive latency Burst size and type ODT resistance values Refresh timings (Auto refresh)

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COMMAND PATH CONT

CHALLENGES Fixed length burst write/read On-The-Fly burst write/read Multiplexing of row and column address Activate logic Parameter in the MRS register set Write leveling logic Fixed burst size SOLUTIONS Implemented Fixed length burst write/read Achieved using ACTIVE and READ/WRITE command Redesigned ZQCL counter Identified and hardcoded Disabled Respective bits of MRS were changed

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COMMAND CONTROLLER
Purpose
Acts as the heart of the module Responsible for taking care of all the latencies of the memory Issues refresh, activate, precharge, read and write commands to the command path after the wait latencies Takes care of issuing device ready signal and command acknowledgement signal to the AXI Acts as the major coordinator with AXI Communicates with the row-status logic to issue precharge and activate commands accordingly Manages read and write data path by issuing appropriate read and write commands
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COMMAND CONTROLLER FSM

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REFRESH

VENDOR SPECIFIC INITIALISATION SEQUENCE

INIT DONE REFRESH DONE BURST DONE

WAIT_tRC REFRESH TIMER

BURST DONE

IDLE
(WRITE | READ)& (OPENED_ROW)& !MATCH

PRECHARGE
READ & MATCH & !OPENED_ROW

WRITE & (OPENED_ROW)& MATCH

WAIT_tRP
PRECHARGE DONE

READ& (OPENED_ROW)& MATCH

ACTIVATE

WRITE
WAIT_tRCD WAIT_tWR
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READ

ACTIVATE DONE DDR3 CONTROLLER DESIGN

WAIT_tCCD
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COMMAND CONTROLLER CONT

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COMMAND CONTROLLER CONT

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COMMAND CONTROLLER CONT

CHALLENGES To interface with the AXI, device ready and command acknowledgement signals were required NOP was not issued earlier during the wait period Refresh timer value Sensing the read/write command coming from the AXI SOLUTIONS Required signals were added to FSM at the required time Later it was issued to the command path Calculated the exact value based on specification The signal was sensed in the first clock cycle

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WRITE PATH
Purpose The write path should facilitate the writing of data in both posedge and negedge of the clock Should take care of burst length Receives the 32-bit input from the AXI and then divides it according to the burst length and writes into the memory Should provide data strobe signal which indicates to the memory that the data is being written into the memory The strobe should be active for period before and after the transaction of the data transfer

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WRITE PATH CONT

8 8 Temp Reg for DATA Capture

0 1
8 FF

0
8 8

WRITE

0 1
8 FF 8

DQ

select

clk

0 1

DQS

Count > tWPR & count < tWPST

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WRITE PATH CONT

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WRITE PATH CONT

CHALLENGES Not working as per the specification Should accept the data only for one clock cycle SOLUTIONS Introduced NOP during the wait period Used temporary register

Integrating with top module

Testing of write data path with the AXI driver Set-up and hold time violations Write leveling error

Data mask output = 0

Delay was modeled accordingly to get the expected output The data was sent with a delay (Behavioral coding) Corrected by mode register setting

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READ PATH
Purpose
Used to read the data from the memory and provide it to the AXI Reads the data from the memory on receiving the strobe signal (DQS) Similar to the write operation, the read operations reads data in both posedge and negedge of the clock Receives the data from the memory according to the burst length Concatenates the data into a 32-bit output and provides to the AXI Provides a valid signal to the AXI which indicates that the valid data is being transferred
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READ PATH CONT

D D R 3 M e m o r y

8-bit DQ 8-bit 8-bit 8-bit 8-bit

32-bit Data

Data Processing Unit

Data Valid Control Signals DQS

A X I

Control Logic
Read (from FSM) CLK RST_N
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READ PATH CONT

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READ PATH CONT

CHALLENGES
Valid signal to AXI model Following the data strobe signal

SOLUTIONS
Incorporated additional signal Studied the DQS pattern as per the specification

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DDR3 CONTROLLER - TOP

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TASKS COMPLETED
RTL coding of the blocks as per the micro-architecture All the blocks were integrated and testing was done by forcing the values

Timing verification of the initialization sequence as per the reference model

Testing of write operation using AXI driver is in progress

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?
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THANK YOU

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