MSP430 Microcontroller Workshop

Version 1.2

Agenda

Introduction to the MSP430F5xx

5xx Active & Low Power Mode Operation

A Mixed-Signal Application Example Using Hardware Timers to Conserve Power A Fully-optimized ADC12 Routine MSP430 Tools, Resources and Conclusion

Portfolio
2

TI Embedded Processing Portfolio

TI Embedded Processors
Microcontrollers (MCUs) 16-bit ultralow power MCUs 32-bit real-time MCUs

ARM-Based Processors
32-bit ARM Cortex-M3 MCUs ARM Cortex-A8 MPUs

Digital Signal Processors (DSPs) Ultra Low power DSP

DSP DSP+ARM

Multi-core DSP

MSP430
Up to 25 MHz Flash 1 KB to 256 KB Analog I/O, ADC LCD, USB, RF
Measurement, Sensing, General Purpose

C2000 Delfino Piccolo

40MHz to 300 MHz Flash, RAM 16 KB to 512 KB PWM, ADC, CAN, SPI, I2C
Motor Control, Digital Power, Lighting, Ren. Enrgy

ARM Cortex-M3

Stellaris
Up to 100 MHz

ARM Cortex-A8 & ARM9

Sitara

C6000 DaVinci
video processors

C6000
24.000 MMACS

C5000
Up to 300 MHz +Accelerator Up to 320KB RAM Up to 128KB ROM USB, ADC McBSP, SPI, I2C
Audio, Voice

OMAP

300MHz to >1GHz Cache, RAM, ROM USB, CAN, PCIe, EMAC

Industrial computing, POS & portable data terminals

Flash 8 KB to 256 KB USB, ENET MAC+PHY CAN, ADC, PWM, SPI

Connectivity, Security, Motion Control, HMI, Industrial Automation

300MHz to >1Ghz +Accelerator Cache RAM, ROM

Cache RAM, ROM

SRIO, EMAC DMA, PCIe
Telecom test & meas, media gateways, base stations

USB, ENET, PCIe, SATA, SPI

Floating/Fixed Point Video, Audio, Voice, Security, Conferencing

Medical, Biometrics

$0.25 to $9.00

$1.50 to $20.00

$1.00 to $8.00

$5.00 to $20.00

$5.00 to $200.00

$40 to $200.00

$3.00 to $10.00

Software & Dev. Tools

5xx Gen Summary
3

5xx Generation Summary

Ultra-Low Power

230 A/MHz 1.9 A standby mode Wake up from standby in < 5 s Up to 25 MHz 8 MHz across entire operating range (1.8 - 3.6 V) 1.8V ISP flash erase & write Fail-safe, flexible clocking system Integrated LDO, BOR, WDT+, RTC Multi-channel DMA supports data movement in standby mode More connectivity: USB, RF AES encryption, RTC on backup battery User-defined Bootstrap Loader Industry-leading code density

Increased Performance

Innovative Features

MSP430 Generations
4

MSP430 Generations
1xx
Basic Clock System Core voltage same as supply voltage 16-bit CPU GPIO

2xx
Basic Clock System + Core voltage same as supply voltage 16-bit CPU, CPUX GPIO w/ pull-up and pull-down N/A Software RTC USCI, USI DMA up to 3-ch MPY16 ADC10,12 4-wire JTAG, some devices with Spy-Bi-Wire

4xx
FLL, FLL + Core voltage same as supply voltage 16-bit CPU, CPUX GPIO

5xx
Unified Clock System UCS Programmable Core Voltage with integrated PMM 16-bit CPUXV2 GPIO w/pull-up and pull-down, drive strength CRC16 True 32-bit RTC w/Alarms USCI, USB, RF DMA up to 8-ch MPY32 ADC12_A 4-wire JTAG and Spy-Bi-Wire

N/A Software RTC USART DMA up to 3-ch MPY16 ADC10,12 4-wire JTAG

N/A Software RTC with Basic Timer, Basic Timer + RTC USART, USCI DMA up to 3-ch MPY16, MPY32 ADC12 4-wire JTAG

MSP430 Generations
5

MSP430 Generations
Category
CPU Clock (max) Active Current (@ 3.0V, typical) 16MHz
515uA @ 1MHz 4.2mA @ 8MHz 9.1mA @ 16MHz

2xx
8MHz

4xx
25MHz
600uA @ 1MHz 4.8mA @ 8MHz N/A

5xx
290uA @ 1MHz 1.84mA @ 8MHz 230 uA/MHz 8.90mA @ 25MHz

120KB / 8KB (Flash / RAM) Wake-up Time From LPM3 1us

120KB / 8KB (Flash / RAM) 6us

256KB / 16KB (Flash / RAM) 5us

Standby LPM3 Current

LPM4 Current Flash ISP Minimum DVCC

0.9 1.1uA
0.1uA 2.2V

1.1 2.5uA
0.1uA 2.7V

1.9uA (RTC, WDT, SVS enabled)

1.2uA (LPM4) / 0.1uA (LPM4.5) 1.8V

Port I/O Interrupt Capability

Prog. Port Pin Drive Strength

P1/P2
N/A

P1/P2
N/A

P1/P2 Some devices also P3/P4

All port pins

Prog. Pull-ups / Pull-downs

12-bit A/D Internal Reference Current 12-bit A/D Active Conversion Current Available MCLK Sources

All port pins

500 uA 800 uA DCO LFXT1 XT2 (if available) VLO N/A

N/A
500 uA 800 uA FLL LFXT1 XT2 (if available)

All port pins

100 uA* 150 uA* FLL LFXT1 / XT1 XT2 (if available) VLO REFO

UCS

Available FLL Reference Clocks

LFXT1

LFXT1, REFO, & XT2 (if present)

* 2xx, 4xx ADC12; 5xx - REF & ADC12_A

6

Roadmap

MSP430 Roadmap
FR57xx Device Production Development
100+ devices

F6/563x
BGM, Catalog

FRAM

F53xx
Gen Purpose

F550x
USB

F51x2 2xx-Catalog
16 MIPS 120 kB Flash 8 kB RAM 500 nA Standby 1.8 3.6V

F261x F241x F23x-F24x F23x0 F23x0 F22xx F21x2 F15x-F16x F13x-F14x F12xx F44x Fx42x Fx42x0 F41x FE42x2 F41x2

Lighting

L092
0.9V Native

F552x
USB

CC430
RF

The New Generation

5xx-6xx
25MIPS 256 kB Flash 16 kB RAM 1.8 3.6V FRAM, USB, RF 6xx: LCD Controller 160 uA/MIPS

G = Value Line F = Flash FR = FRAM F20xx G2xx1

F541x

F543xA

F21x1 G2xx5

FG461x Fx43x Fx47x F47x4 F43x

F471xx
100+ devices

G2xx2
75+ devices

F11xx

4xx: LCD
16 MIPS 120 kB Flash 8 kB RAM LCD Controller, 160 segments 1.8 3.6V

1xx-Catalog
8MIPS 60 kB Flash 10 kB RAM 1.8 3.6 V

CPU
7

5xx MSP430Xv2 Orthogonal CPU

C-compiler Memory

friendly

address range increased to

1MB
CPU

registers increased to 20-bits

instructions

Address-word

Direct 20-bit CPU register access Atomic (memory-to-memory) instructions

Instruction

compatible with previous

CPU
Cycle

count optimization word allows all instructions

Extension

Direct access to 1MB address space

Bit, byte, word and address-word data Repeat instruction function

UCS
8

Unified Clock System (UCS)

Six independent clock sources

Low Freq

LFXT1 VLO REFO XT1 XT2 DCO clock

32768 Hz crystal 10 kHz 32 kHz 4 32 MHz crystal 4 32 MHz crystal FLL multiple of reference

High Freq

FLL references are divisible

LFXT1 / XT1 REFO XT2

ACLK / SMCLK / MCLK tree is fully orthogonal Clocks on demand MODOSC provided to modules

Flash controller & ADC12_A

Operating Modes
9

5xx Operating Modes

SVS protection for just 200 nA Active Mode 230 uA/MHz

CPU active Fast Peripherals Enabled 32 kHz Peripherals Enabled - RTC CPU disabled Fast Peripherals Enabled 32 kHz Peripherals Enabled RTC CPU disabled Fast Peripherals Disabled 32 kHz Peripherals Enabled

LPM0 70 uA

LPM3 1.9 uA

RTC, Watchdog & SVS protection

LPM4 1.2 uA

All clocks disabled Wake on interrupt Regulator & all clocks disabled No RAM retention BOR on nRST/NMI or Port I/O

LPM4.5 (LPM5) 100 nA

Operating Range
10

5xx Voltage vs. Frequency Operating Range

25MHz peak performance More performance across VCC range

Flash ISP @ min. VCC 8MHz @ min. VCC Up to 25MHz @ 2.4V-3.6V

Programmable VCORE maximizes power efficiency Lowering VCC or VCORE reduces system current

Mem Map
11

5xx Memory Map

Page-free 20-bit addressing User-definable Boot Strap Loader

RAM starts at 0x1C00

Always a contiguous block

Beginning of MAIN flash moves according to RAM Vector table starts at 0xFF80

SYS
12

5xx Peripherals The SYS Module

Reset Interrupt Vector Generator

Brownout (BOR) (highest priority) RST/NMI (POR) DoBOR (BOR) Port_wakeup (BOR) Security violation (BOR) SVSL (POR) SVSH (POR) SVML_OVP (POR) SVMH_OVP (POR) DoPOR (POR) WDT time out (PUC) WDT key violation (PUC) KEYV flash key violation (PUC) PLL unlock (PUC) PERF peripheral/config area fetch (PUC)

Generates a constant that maps to the cause of last reset Simplifies reset handling

Manages non-maskable interrupts

Reset events NMIs split into SYSNMI & UNMI SYSNMIs have higher priority Separate interrupt vectors

Factory application data is considered part of the SYS module

Factory calibration data and peripheral discovery table

GPIO
13

5xx Peripherals GPIO

Initial state of GPIO pins is a digital input

Port registers allow for different configurations

PxDIR direction (input vs output)

PxREN enables internal pull-up/pull-down resistors (input)

PxDS enables additional drive strength (output) PxIE Interrupt enable PxIES Interrupt edge select PxIFG Interrupt flag registers

Select ports have interrupt capabilities

GPIO functionality is multiplexed with analog and digital peripheral functions

PxSEL Peripheral function select

Port Map Module

14

5xx Peripherals Port Map Module

Port mapping allows for additional digital signals to be mapped to one or several output pins.

PM_xxx denotes a port-mappable signal Datasheet specifies which ports can be mapped

By default, single configuration per PUC reset

Port Mapping Reconfigure bit (PMRECNFG) allows for runtime re-configurations

Port mapping configuration is password protected Available on select MSP430 families. (Check the datasheet)

USCI
15

Universal Serial Communications Interface

USCI - New standard MSP430 serial interface Auto clock start from any low power mode Two independent communication blocks Asynchronous communication modes UART standard and multiprocessor protocols UART with automatic Baud rate detection (LIN support) Two modulators support n/16 bit timing IrDA bit shaping encoder and decoder Synchronous communication modes SPI (Master & Slave modes, 3 & 4 wire) I2C (Master & Slave modes)
UxRXBUF Receiver Shift Register UCLKI ACLK SMCLK SMCLK URXD SOMI Baud-Rate Generator STE SIMO Transmit Shift Register UxTXBUF UTXD

Clock Phase and Polarity

UCLK

LCD and AES

16

5xx Peripherals LCD_B & AES128

LCD distinguishes 6xx from 5xx Static, 2-, 3- or 4-mux displays Supports up to 196 LCD segments Blinking of individual segments Regulated charge pump Software-driver contrast control Integrated drivers to decouple LCD load from the bias generation

Encryption and decryption according to AES FIPS PUB 197 with 128-bit key Key expansion for en- and decryption Off-line key generation for decryption AES ready interrupt flag
USB

17

5xx + USB

Single-chip USB solution Just add USB connector & TI-supplied USB API software for the most common device classes (CDC/HID/MSC) USB + analog + ultra-low-power
+3.3V

VUSB +5V VBUS USB Module

DVCC

Power Supply CPU & Supervision RAM DMA 32x32 MPY CRC 16 Serial Comms Flash

PUR DD+

Timers RTC Clocks 12-bit ADC

Comparator

ESD

TPD2E001DRL
ESD Protection Diode Array

4MHz

CC430
18

5xx + Low-Power RF The CC430

CC430
Supports: 300-348MHz, 387- 464MHz and 779-928MHz

Low Power RF IC
Radio Frequency

MSP430 MCU
Application & Protocol processor

Low-power RF SoC

Low Power < 1 GHz RF Transceiver

High sensitivity Low current consumption Excellent blocking performance Flexible data rate & modulation format Backwards compatible

MSP430 5xx MCU

Ultra-low power High analog performance High level of integration Ease of development Sensor interface

Emulation
19

5xx Embedded Emulation

Used for in-system programming and emulation JTAG access can be locked using SW no fuse JTAG pins serve as 4 x pin GPIO port (Port J) Support for both 4-wire and 2-wire Spy-Bi-Wire Compatible with existing MSP430 tools

Emulation
20

5xx Embedded Emulation

Simplifies in-system debugging and reduces development time

Up to 8 hardware breakpoints with complex triggering capabilities 40-bit wide CPU cycle counters in hardware JTAG Mailbox system provides direct interface to the CPU during

Debugging (Run-time data UART RTDX) Programming / Test

State Storage: non-intrusive trace buffer for data and address bus (e.g., instruction fetch)

Block Diagram
21

MSP430F5438A Block Diagram

MSP-EXP430F5438
22

MSP-EXP430F5438

Easy power select

USB, JTAG, Battery

USB communication Microphone Filtered PWM audio output

Active, selectable gain Headphone compatibility

2-axis accelerometer Dot-matrix LCD (138x110)

Integrated backlight

1 x 5-direction switch 2 x push-button switches RF Interface

CCxxxx EVMs EZRF I/F (6 & 18- pin)

Please ensure 2 x AA batteries are in place on the back of the board

Load your F5438A into the socket in the appropriate orientation

CCS

23

Code Composer Studio 4.1

Code Composer Studio v4.1: A single development platform for all TI processors
Enhancements:
Speed Code

size improvements manager for all TI MCUs

Auto-updating License Support

Only $495 for MCU Edition FREE 16KB-limited edition

Community Support
24

Extensive Community Support

E2E Community
Videos,

Processor Wiki
Growing

Blogs, Forums Extensive community support and idea exchange Global customer support http://e2e.ti.com

collection of technical wiki articles Tips & tricks, common pitfalls, and design ideas http://wiki.msp430.com

Lab_1
25

Lab_1: Blink the LED

FET

Blink the LED with C code running on the MSP430F5438A

Agenda
26

Agenda

Introduction to the MSP430F5xx

5xx Active & Low Power Mode Operation

A Mixed-Signal Application Example Using Hardware Timers to Conserve Power A Fully-optimized ADC12 Routine MSP430 Tools, Resources and Conclusion

ULP Best Practices

27

Ultra Low Power (ULP) Operation Best Practices

Power-efficient MSP430 apps:

Minimize instantaneous current draw Maximize time spent in low power modes

The MSP430 is inherently low-power, but your design has a big impact on power efficiency Proper low-power design techniques make the difference

ULP Best Practices

28

ULP Operation Best Practices

Power draw increases with

Vcc CPU clock speed (MCLK) Temperature

Slowing MCLK reduces instantaneous power, but usually increases active duty cycle

Power savings can be nullified The ULP sweet spot that maximizes performance for the minimum current consumption per MIPS: 8 MHz MCLK

Full operating range (down to 1.8V)

5xx has integrated LDO with variable output voltage Optimize core voltage for chosen MCLK speed

ULP Best Practices

29

ULP Operation Best Practices

Digital input pins subject to shoot-through current

Input voltages between VIL and VIH cause shoot-through if input is allowed to float (left unconnected) Driven as outputs Be driven at Vcc/ground by an external device Have a pull-up/down resistor

Port I/Os should

ULP Clock Control (UCS)

30

ULP Clock Control: Unified Clocking System (UCS) Defaults

FLLREFCLK = XT1CLK ACLK = XT1CLK MCLK = DCOCLKDIV SMCLK = DCOCLKDIV DCOCKLDIV = DCOCLK / 2 DCO_freq ~= 2 MHz, so

MCLK_freq ~= 1 MHz SMCLK_freq ~= 1MHz

ULP Clock Control (FLL)

31

ULP Clock Control: The 5xx Frequency Locked Loop (FLL)

FLLREFCLK sources:

32 kHz internal REFO

LFXT1 / XT1 crystal oscillator

XT2 crystal oscillator

DCO frequency equation

fDCO = (fFLLREFCLK / n) * (N + 1) * D

n = FLLREFDIV N = FLLN D = FLLD

ULP Clock Control (DCO)

32

ULP Clock Control: The 5xx Digitally Controlled Oscillator (DCO)

DCO ranges from 200 kHz 60 MHz

RSEL bits select the range DCO bits set one of 32 taps in each range MOD bits mix two frequencies fDCO and fDCO+1 to produce DCOCLK

PMM
33

Power Management Module (PMM)

Integrated Low Dropout (LDO) regulator: VCC VCORE VCORE is programmable to four levels Brown Out Reset (BOR) is always ON PMM is password protected

Unlock: Lock:

PMMCTL_H = 0xA5 PMMCTL_H = 0x00

Integrated Supervision and Monitoring

Monitoring provides interrupts on low voltage condition

Supervision generates Power On Reset (POR) on low voltage condition Vcc domain is referred to as the high-side (SVSH, SVMH) Core voltage domain is referred to as the low-side (SVSL, SVML) 200nA - Normal Performance Mode (20 us response time) 2 uA - Fast Performance Mode (2 us response time)
Vcore

Accurate voltage supervision

34

Steps to Change VCORE

Increasing the Core Voltage

1. 2. 3. 4.

Change the low-side monitor threshold Change the core voltage level Wait until the core voltage level is reached Change supervisor threshold to match the monitor level

Decreasing the Core Voltage

5. 6.

Decrease supervisor and monitor levels Decrease the core voltage level

Supervision and Monitoring

35

Voltage Supervision & Monitoring

SVS / SVM disabled
SVS / SVM disabled Zero-power BOR protection is ALWAYS ON 5 us wakeup from LPM2,3,4 +0 uA active & LPM2,3,4 current consumption

High-side Full Performance Mode

High-side Full Performance Mode Low-side SVS / SVM disabled +4uA active current consumption +0uA LPM2,3,4 current consumption Automatic high-side protection when CPU is active

Maximum Robustness
Fast Performance Mode 5 us wakeup from LPM2,3,4 +8 uA active & LPMx current consumption

5 us wakeup from LPMx

Power on Default Mode

High-side Fast Performance Mode

High-side Fast Performance Mode Low-side SVS / SVM disabled 5 us wakeup from LPM2,3,4 +4 uA active & LPM2,3,4 current consumption Automatic high-side protection when CPU is active

Normal Performance Mode +800 nA active current consumption 0 nA LPM2,3,4 current consumption

150 us wakeup from LPMx Current

Entering LPMs
36

Entering Low Power Modes

Interrupts and Stack

37

Interrupts and the Stack

Entering Interrupts Any currently executing instruction is completed. The PC, which points to the next instruction, is pushed onto the stack. The SR is pushed onto the stack. The interrupt with the highest priority is selected The interrupt request flag resets automatically on single-source flags. Multiple source flags remain set for servicing by software. The SR is cleared. This terminates any low-power mode. Because the GIE bit is cleared, further interrupts are disabled. The content of the interrupt vector is loaded into the PC; the program continues with the interrupt service routine at that address.

Intrinsics
38

Using Intrinsic Functions to Program the Status Register (SR)

Intrinsic Functions:
__bic_SR_register(LPM3_bits); __bic_SR_register_on_exit(LPM3_bits); __bis_SR_register(LPM3_bits + GIE); __bis_SR_register_on_exit(unsigned short a); __get_SR_register(void); __get_SR_register_on_exit(void); __enable_interrupts( ); __disable_interrupts( );

Other useful intrinsics:

__no_operation(); __delay_cycles(1000000); __bcd_add_short( short, short ); __bcd_add_long( long, long ); __even_in_range( );

Refer to intrinsics.h or compiler documentation

Fail-Safe

39

Fail-Safe Behavior & Clock Requests

LFXT1 reverts to REFO HFXT1 & XT2 revert to DCO On startup, LFXT1 will fail because quartz crystals are not instant-on Clearing the fault flags allows expected default operation

Modules place clock requests to the system clocks LPM3 entry can be prevented if a module requires SMCLK to operate properly User must be aware of the clocks required in the system.

Available Oscillators
40

ULP Review of Available Oscillators

Clock Frequency Precision Current Draw Crystal Required

High-Frequency
DCO HFXT1/ XT2 MODOSC
RTC

100kHz 60MHz 4 - 32MHz 5MHz 32kHz ~10kHz 32kHz

Low High n/a

Low-Frequency

60uA 260uA @ 12MHz n/a 300nA 60nA 3uA X X

LFXT1 VLO REFO

High Low Medium/High

Lab_2
41

Lab2: Active & ULP Mode Operation

Learn and understand how two key modules (PMM & UCS) achieve ultra low power operation by measuring the power consumption of various Active and LPM3 scenarios

Using an ammeter and measure the current through the PWR1 jumper
FET

Agenda
42

Agenda

Introduction to the MSP430F5xx

5xx Active & Low Power Mode Operation

A Mixed-Signal Application Example Using Hardware Timers to Conserve Power A Fully-optimized ADC12 Routine MSP430 Tools, Resources and Conclusion

Comparator
43

Comp_B Analog Comparator

Inverting and noninverting terminal input multiplexer Software-selectable RC filter for the comparator output Output provided to Timer_A capture input Interrupt capability Selectable reference voltage generator and voltage hysteresis generator Reference voltage input from shared reference Ultra-low-power comparator mode

ADC12_A
44

ADC12_A Features

12-bits, SAR, 200 ksps+ Timer_A/B, software triggers Up to 12 external input

Conversion Modes:

Single Sequence Repeat-single

Repeat-sequence

Internal/external reference 16 conversion result storage Input range: Vss Vref

ADC12_A

45

ADC12_A Enhancements

VREF settling time

75us vs. 17ms

Tighter temp coefficient on internal reference

50ppm vs. 100ppm Selectable speed vs power ADC12_A core is only enabled when needed

Lower power modes

Higher clock dividers for faster system clocks ~6x lower current than ADC12

150uA for ADC active 100uA for 2.5V VREF active

Temp and Vcc

46

ADC12 Temperature & Vcc Sampling

On-chip temperature sensor channel On-chip Vcc/2 channel The temperature sample period > 30 us Temp sensor offset voltage is large and must be calibrated

2-point calibration data inside Factory Application Data

Conversion Memory and Control

47

ADC12 Conversion Memory & Control

Each memory register is configurable

EOSx Identifies the end of a sequence-of-conversions.

When the conversion result is written into the EOS ADC12MEMx register, the interrupt will be triggered.

SREFx Selects the reference (internal, external, etc)

INCHx Selects input channel for the ADC12MEMx register

Input channels can be mixed for a sequence-ofconversions

Lab 3 Flowchart

48

Lab 3: Brute-force Temperature Sampling

Lab 3 code
49

Lab 3.c Code

while(1){ REFCTL0 |= REFON; __delay_cycles(85); ADC12CTL0 |= ADC12ENC+ADC12SC; // Enable internal reference // Settling time for reference // (Re)enable & trigger conversion

// Poll IFG until ADC12MEM1 loaded signifying sequence is complete while(!(ADC12IFG & BIT1)); ADC12CTL0 &= ~ADC12ENC; REFCTL0 &= ~REFON; temp_temp = ADC12MEM0; temp_vcc = ADC12MEM1; // // // // Disable conversions to configure REF Disable internal reference Read ADC12 temperature conversion Read ADC12 Vcc/2 conversion

// Calculate temperature in degrees Celsius & format display string accordingly ... // Calculate temperature in degrees Fahrenheit & format display string accordingl ... // Calculate Vcc in volts & format display string accordingly ... /* Initialize serial communication module to send data over USB */ halUsbInit(); halUsbSendString(&USB_string[0],USB_STRING_LEN+2); halUsbShutDown(); // Shut down USB to enter sleep mode
__delay_cycles(2200000); } } // Delay 2 seconds

Alphabet Soup
50

Decoding the Alphabet Soup

void halADCInit(void){ ADC12CTL0 = ADC12SHT0_7 + ADC12ON + ADC12MSC; ADC12CTL1 = ADC12CONSEQ_1+ADC12SHP; ADC12MCTL0 = ADC12SREF_1 + ADC12INCH_10; ADC12MCTL1 = ADC12SREF_1 + ADC12INCH_11 + ADC12EOS; REFCTL0 |= REFMSTR + REFVSEL_1; }

(msp430x54xA.h file)

(User Guide)
Lab 3 Power
51

Lab 3 Power
540uA

Current

Active ADC = 150uA 1.5V Internal Reference = 100uA

Active ADC = 150uA

390uA 290uA
75us Active MCLK @1MHz=290uA 80us

Time
2 seconds until next Sample

CPU

is ALWAYS ON (~290 uA) Delay between ADC12 samples executed by software

__delay_cycles(2200000);

ADC12

handled completely in software

Reference settling, Software trigger, IFG polling

Lab 3

52

Lab 3: Using the ADC12

Use ADC12 integrated temperature sensor Set up ADC12 to perform a single conversion Loop continuously, converting to Degrees F and C in software Touch the F5438A with a finger to change the temperature Open a watch window in the debugger to see the temperature values

FET

Agenda
53

Agenda

Introduction to the MSP430F5xx

5xx Active & Low Power Mode Operation

A Mixed-Signal Application Example Using Hardware Timers to Conserve Power A Fully-optimized ADC12 Routine MSP430 Tools, Resources and Conclusion

Timer Architecture
54

Timer Architecture

Asynchronous 16-bit timer/counter

Continuous, up-down, up count modes

Multiple capture/compare registers

PWM outputs
Interrupt vector register for fast decoding Can trigger DMA transfer On all MSP430s

Timer Modes
55

Timer Counting Modes

Interrupts
56

Timer_B Interrupts
The Timer_B Capture/Comparison Register 0 Interrupt Flag (TBCCR0) generates a single interrupt vector: TBCCR0 CCIFG TIMERB0_VECTOR

No handler is required

TBCCR1-6 and TB interrupt flags are prioritized and combined using the Timer_B Interrupt Vector Register (TBIV) into another interrupt vector

TBCCR1 CCIFG TBCCR2 CCIFG TBIFG

Your code must contain a handler to determine which Timer_B interrupt triggered The same applies to Timer_A
57

TBIV

TIMER_B1_VECTOR

B vs A

Timer_B vs Timer_A

Default function identical to Timer_A 8, 10, 12, or 16-bit timer or counter (16-bit only for Timer_A) Outputs double-buffered for simultaneous loading CCRx registers can be grouped for simultaneous updates Tri-state function from external pin

Lab 4 Flowchart
58

Lab 4 Temperature Measurement with Timer

Main loop Timer CCR0 ISR

Lab 4 Power
59

Lab 4 Power
540uA Current

Active ADC = 150uA 1.5V Internal Reference = 100uA

Active ADC = 150uA

390uA 290uA
75us Active MCLK @1MHz=290uA 80us

2.1uA Time
2 seconds until next Sample

CPU is in LPM3 most of the time Delay between ADC12 samples handled by hardware ADC12 handled completely in software

Reference settling, Software trigger and IFG polling

Lab 4

60

Lab 4: Using Hardware Timers to Conserve Power

Perform same task as previous lab exercise, but use LPM3 to reduce power consumption Timer B will be used to replace the 2 second software delay

FET

Agenda
61

Agenda

Introduction to the MSP430F5xx

5xx Active & Low Power Mode Operation

A Mixed-Signal Application Example Using Hardware Timers to Conserve Power A Fully-optimized ADC12 Routine MSP430 Tools, Resources and Conclusion

Timer Output
62

Timer Output Continuous Mode

Each CCRx register can be used in the different timer modes to generate interrupt flags Independent PWM frequencies with different duty cycles can be automatically generated in continuous mode using CCR0 and CCR1+ A new interrupt (TAIFG or TBIFG) occurs on every rollover of the timer Continuous Mode

Timer Triggering ADC12

63

Timer-Triggering the ADC12

Power Optimization:

Currently: Timer delays for 2 seconds, software ADC12 trigger Optimization: Timer delays for 2 seconds, then: [1] Enables reference on TBIFG rollover

[2] Triggers ADC12 sample/conversion using TBCCR1 output

SHP bit selects whether the sample time is set by:

TBCCR1 output (SHP = 0) SHT0x * ADC12CLK [ lab uses SHT0x * ADC12CLK cycles (192 x 1/5MHz ~= 40 us)]

Time between TBIFG and TBCCR1 must be > 75 us for 2.0V REF to stabilize

Timer Interrupts
64

Timer_B Interrupts
The Timer_B Capture/Comparison Register 0 Interrupt Flag (TBCCR0) generates a single interrupt vector: TBCCR0 CCIFG TIMERB0_VECTOR

TBCCR1-6 and TB interrupt flags are prioritized and combined using the Timer_B Interrupt Vector Register (TBIV) into another interrupt vector

TBCCR1 CCIFG TBCCR2 CCIFG TBIFG TBIV

TIMER_B1_VECTOR

Handler
65

TB0IV Handler Example

TB0IV 0 0 0 0 0 0 0 0 0 0 0 x x x x 0 15 0 Source TAIV Contents No interrupt pending 0 TBCCR1 CCIFG 02h TBCCR2 CCIFG 04h Reserved 06h Reserved 08h TBIFG 0Ah Reserved 0Ch Reserved 0Eh 0xF814 0xF818 0xF81A 0xF81C 0xF81E 0xF820 0xF822 0xF824 0xF828 0xF82A 0xF82E 0xF830 0xF834 add.w reti jmp jmp reti reti jmp xor.b reti xor.b reti xor.b reti &TB0IV,PC 0xF824 0xF82A

Highest-priority IFGs cleared when TB0IV is read

#pragma vector = TIMER0_B1_VECTOR __interrupt void TIMER0_B1_ISR(void) { switch(__even_in_range(TB0IV,10)) { case 2 : // TBCCR1 CCIFG P1OUT ^= 0x04; break; case 4 : // TBCCR2 CCIFG P1OUT ^= 0x02; break; case 10 : // TBIFG P1OUT ^= 0x01; break; } }

0xF830 #0x4,&P1OUT
#0x2,&P1OUT #0x1,&P1OUT

Interrupt Control
66

ADC12 Interrupt Control

Power

optimization:
Polling for ADC12MEM1IFG Enable ADC12MEM1IFG interrupts & wake CPU only to handle conversion data

Currently: Optimization:

ADC12

Interrupt Enable (ADC12IE) bits enable interrupt request on a write to the respective ADC12MEMx register ADC12MEM1 has EOS set, so interrupt will be requested after the sequence of temperature and vcc/2 conversions is complete Reading the ADC12MEMx register clears the respective interrupt flag
ADC12IFG1 Handler
67

How to Write the ADC12IFG1 Handler

switch(__even_in_range(ADC12IV,36)) { case 0: break; // No interrupt case 2: break; // Overflow case 4: break; // Time overflow case 6: break; // ADC12MEM0IFG case 8: // ADC12MEM1IFG Disable REF & ADC12 samples; Read ADC12MEM0 & ADC12MEM1; Exit active to main( ); break; case 36: break; }

Lab 5 Code
68

Lab 5 Code
Main

ADC12MEM1 ISR

Timer Overflow ISR

Lab 5 Power
69

Lab 5 Power
Current 252uA

Active ADC = 150uA 1.5V Internal Reference = 100uA

Active ADC = 150uA

102uA 2.1uA Time

2 seconds until next Sample

CPU is no longer active during:

ADC12 reference settling ADC12 sampling

ADC12ISR wakes CPU for very short time:

Entry/exit to ISR Disables the reference Stores the ADC12MEM0 & ADC12MEM1 values Wakes active on exit from LPMx
Lab 5

70

Lab 5: Fully Automated ADC12 Routine

Perform same task as previous lab exercise, but use Timer B in continuous mode to trigger TBIFG interrupt and generate TBCCR1 output Time between TBIFG and TBCCR1 will automatically handle internal reference settling time

FET

Agenda
71

Agenda

Introduction to the MSP430F5xx

5xx Active & Low Power Mode Operation

A Mixed-Signal Application Example Using Hardware Timers to Conserve Power A Fully-optimized ADC12 Routine MSP430 Tools, Resources and Conclusion

IAR
72

IAR for MSP430

CCS
73

Code Composer Studio 4.1

Code Composer Studio v4.1: A single development platform for all TI processors
Enhancements:
Speed Code

size improvements manager for all TI MCUs

Auto-updating License Support

Only $495 for MCU Edition FREE 16KB-limited edition

eZ430 Tools
74

The eZ430 Family of MSP430 Tools

The eZ430 is a tradition of low-cost, easy-to-use tools for MSP430

Options include RF, energyharvesting, RFID, even a wireless sports watch development kit!

FETs
75

Programming Tools

Parallel FET

Supports ALL MSP430 devices Supports 4-Wire JTAG mode only Fixed output voltage of 2.8V No JTAG fuse blow Simple hardware circuit, possible to implement as part of a product

USB FET

Supports ALL MSP430 devices Supports 4-Wire and 2-Wire (Spy-Bi-Wire) JTAG Adjustable output voltage: 1.8 - 3.6V, 100mA JTAG fuse blow Fast operation
Gang Programmer

76

Gang Programmer GANG430

Target Boards
77

Target Boards for Device Programming

100-pin target board exclusive to the F543x(A) / F541x(A) devices Development board with 100-pin TSSOP (PW) ZIF socket (MSPTS430PZ5x100) All pins brought out to pin headers for easy access Programming via JTAG, Spy-bi-wire or BSL A FET board exists for most variants of MSP430 Only $49

MSP-EXP430FG4618
78

MSP-EXP430FG4618 Experimenter Board

Connector for CC1100/CC1101/ CC2500/CC2420 EMs Includes support for the CC2480 ZigBee Processor

SW examples and function library available at www.ti.com/ccmsplib

Software Tools

79

MSP430 Software Tools

Wireless Networking Protocols

Z-Stack (CC2520 + MSP430F5438 ZigBee) TI-MAC SimpliciTI (on MSP430 MediaWiki) DASH7 Wireless M-Bus 6LoPAN

Example Code for the MSP-EXP430F5438 Experimenter Board (www.ti.com/msp430tools)

Drivers for hardware peripherals, LCD, USB conn. uC-OSII IAR PowerPac Salvo FreeRTOS
www.ti.com

Operating Systems

80

www.ti.com/msp430

Users Guides
Datasheets Code Libraries

100+ Application Reports

1000+ Code Examples Product Brochure Latest Tool Software 3rd Party Listing Silicon Errata

Summary
81

5xx Generation Summary

Ultra-Low Power

230 A/MHz 1.9 A standby mode Wake up from standby in < 5 s Up to 25 MHz 8 MHz across entire operating range (1.8 - 3.6 V) 1.8V ISP flash erase & write Fail-safe, flexible clocking system Integrated LDO, BOR, WDT+, RTC Multi-channel DMA supports data movement in standby mode More connectivity: USB, RF AES encryption, RTC on backup battery User-defined Bootstrap Loader Industry-leading code density

Increased Performance

Innovative Features

Dont Forget
82

Dont Forget!

Take your workshop handouts home with you

Fill out the evaluation form on line if possible (use paper forms otherwise)
This material is available on-line:
http://processors.wiki.ti.com/index.php/MSP430_5xx_One_Day_Workshop

Thank you for attending

Have a safe trip home

83

84