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BY Prof. Y. P. Jadhav Physics Department Smt. CHM college, Ulhasnagar - 3

Tri-state Devices
Microcomputer contains
at least one microprocessor and large number of interfacing devices (Peripheral or ICs or Chips). These devices are connected to microprocessor through a bus oriented system. The microprocessor can access (communicate with) only one (IO or memory) device at a time; hence all other devices (chips) must be disconnected. But all the devices cannot be disconnected within very short duration (1 sec) physically. Hence tri-state logic is used to disconnect unwanted chips or devices from the bus electrically, but not physically.
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Tri-state logic devices Three states logic 1, logic 0 and high impedance state (logic z). It has third input line called Enable, enabled - device works in its normal way. disabled - the logic device goes in to high impedance state-as if it is disconnected from the system. Tri-state logic is used to make devices compatible with bus oriented system.

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Input Enable E/G

Output

Input Enable E / G

Output

Truth tables:

E I/P O/P 0 X Logic z 1 0 1 0 1 1

I/P X 0 1

O/P Logic z 1 0

1 0 0

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Buffer
the logic device which amplifies the current or power. It has one input and one output line. non inverting or inverting output tri-state devices to facilitate their uses in bus oriented system. Use - primarily to increase the driving capability of a logic circuit (compared to logic gate) therefore also knows as driver. Two types:
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Unidirectional Bidirectional

Input Enable

Output

Unidirectional buffer:
Vcc
20 2 4 6 8 1A 4 11 13 15 17
2Y4 2A4 2A1 1Y4 2Y1 1A1

1G
1 1Y 1 18 16 14 12 9 7 5 3

IC 74LS 224 - an octal tri-state non inverting unidirectional buffer. also known as line driver or line receiver. used as a driver for the address bus to improve driving capability of address lines. two groups of four buffers with tri-state output and controlled by two active low enable lines. Each buffer is capable of sinking 24 mA and sourcing 15 mA of current.

10 GND

19

2G

74 LS 240 is another example of tri-state buffer with inverted output.

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 74LS244 is Octal Buffer and Line Driver designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density. Hysteresis at Inputs - to Improve Noise Margins 3-State Outputs - to drive Bus Lines or Buffer Memory Address Registers Input Clamp Diodes - to limit High-Speed Termination Effects

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Bidirectional buffer:
Vcc A1 A2 A3 A4 A5 A6 A7 A8
2
3 4 5 6 7 8 9 1 19 20

GND
10

The data bus of microprocessor is bidirectional therefore it requires a buffer that allows data to flow in both directions.
B1 B2 B3 B4 B5 B6 B7 B8

18
17 16 15 14 13 12 11

bidirectional buffer 74LS 245. also called octal bus transceiver. The direction of data flow is controlled by the pin DIR.
Enable L L H
G

DIR L H X

Operation B data to A bus A data to B bus Isolation

DIR
Direction Control

G
Enable

Another example - Intel 8286 high capability than 74LS245. These two buffers are not pin compatible.
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Bidirectional buffer 74LS 245

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FUNCTIONAL DESCRIPTION OF OCTAL BUS TRANSCEIVER The SN54/74LS245 is an Octal Bus Transmitter/Receiver designed for 8line asynchronous 2-way data communication between data buses. Direction Input (DIR) controls transmission of Data from bus A to bus B or bus B to bus A depending upon its logic level. The Enable input E can be used to isolate the buses. Hysteresis Inputs to Improve Noise Immunity 2-Way Asynchronous Data Bus Communication Input Diodes Limit High-Speed Termination Effects

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Decoder
A decoder is a circuit that changes a code into a set of signals. used to convert one form of binary code into another form. it is a multi-input multi-output combinational logic device. For a particular input combination only one output line is activated. is a logic device that identifies each combination of the input signal and decodes it into a proper output line. decoder having n input lines will decode maximum m = 2n lines types - 2-4, 3-8, 4-16, 4 -10 (BCD) etc.
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uses: interfacing I/O peripherals and memory. built internal to a memory chip to identify individual memory register (location). as an 8-output demultiplexer.

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74LS138 and Intel 8205 are examples of 3-to-8 decoder with active low output lines.

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8 GND
A7 A6 A5 A4 A3 A2 A1

V CC 3 2 1 C

GND

Y7 Y6 Y5 Y4 Y3 Y2 Y1

B 74LS138 U1 A

G2A G2B G1 Y 0 4 5 6

7 9 10 11 12 13 14 15

V CC 3 2 1 A2 A1 A0 E1 E2 4 5

8205 or U1 138

E3 A 0 6

7 9 10 11 12 13 14 15

Enable
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Enable
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FUNCTIONAL DESCRIPTION
The 74LS138 is a high speed 1-of-8 Decoder/Demultiplexer fabricated with the low power Schottky barrier diode process.

V CC 3 2 1 C

GND

Y7 Y6 Y5 Y4 Y3 Y2 Y1

B 74LS138 U1 A

G2A G2B G1 Y 0 4 5 6

7 9 10 11 12 13 14 15

The decoder accepts three binary weighted inputs (A2, A1, A0) and provides eight mutually exclusive active LOW Outputs (O0O7 or Y0Y7).
The LS138 features three Enable inputs, two active LOW (E1, E2) and one active HIGH (E3). All outputs will be HIGH unless G2A and G2B are LOW and G1 is HIGH. The 74 LS138 can be used as an 8-output demultiplexer by using one of the active LOW Enable inputs as the data input and the other Enable inputs as strobes. The Enable inputs which are not used must be permanently tied to their appropriate active HIGH or active LOW state.

Enable

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Multiple enable inputs also allows easy parallel expansion of the decoder device to a 1-of-32 (5 lines to 32 lines) decoder with just four LS138s and one inverter (as shown in figure).

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74LS138 Function Table

Inputs Enable Select
G1 X G2 H C X B X A X Y0 H Y1 H Y2 H

Outputs
Y3 H Y4 H Y5 H Y6 H Y7 H

L
H H H H H H H H
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X
L L L L L L L L

X
L L L L H H H H

X
L L H H L L H H

X
L H L H L H L H

H
L H H H H H H H

H
H L H H H H H H

H
H H L H H H H H

H
H H H L H H H H

H
H H H H L H H H

H
H H H H H L H H

H
H H H H H H L H

H
H H H H H H H L
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Encoder
An encoder is a circuit that changes a set of signals into a code. The encoder is the logic circuit that provides the appropriate code as output for each input signal.

16 4 3 2 1 7 6 5
V CC

8
GND

A2 A1 A0 U1 74LS148

6 7 9

74LS148: an 8 to 3 priority encoder. Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. data inputs and outputs are active at the low logic level. All inputs are buffered
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4 13 3 12 2 11 1 10 0

E0 15 GS 14 E1
5
Enable

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Function Table of 74LS 148

Inputs
E1
H L L L

Outputs
4
X H X X

0
X H X X

1
X H X X

2
X H X X

3
X H X X

5
X H X X

6
X H X L

7
X H L H

A2
H H L L

A1
H H L L

A0
H H L H

GS
H H L L

E0
H L H H

L
L L L L

X
X X X X

X
X X X L

X
X X L H

X
X L H H

X
L H H H

L
H H H H

H
H H H H

H
H H H H

L
L H H H

H
H L L H

L
H L H L

L
L L L L

H
H H H H

Encoders are commonly used - To interface input devices in n-Bit Encoding circuits in Code Converters and Generators Priority encoder - in priority interrupts in computers and microprocessors.

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Latch
In its simplest from, a latch is a data flip-flop
Latch
Input

CLK

D Q U1 7475 G Q

T12
CLK
t1 t2

T23
t3

T34
t4 t5

Input Latch Output Data Latch

Input

PR
U1 7474

Q Q

Data Latch

(a) (b)

CLK

C LR

Positive Edge Triggered

Trigger

Trigger

Output Waveforms of Latch (a) and Positive Edge T riggered Flip-Flop (b)
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A latch is commonly used to interface output devices. Example: 74LS373 - a transparent latch
20 Vcc 3 4 10 GND

1D

D
CLK

1Q 2 2Q 5 3Q 6 4Q 9 5Q 6Q 15
12

It includes eight D latches with tri-state buffers two input signals, Enable (G) and Output Control ( OC )
The Enable is the active high input connected to clock input of the flip-flops. The Output Control is active low, and it enables the tri-state buffers to output data

2D 7 3D 8 4D
13

5D 14 6D
17

74LS373 U1

7D 18 8D

G
11 Enable

OC

7Q 16 8Q 19

1 Output Control

This latch can be viewed as register in a memory chip.

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Function table of 74LS373

20 Vcc 3 4

10 GND

1D

D
CLK

1Q 2 2Q 5 3Q 6 4Q 9 5Q 6Q 15 7Q 16 8Q 19
12

2D 7 3D 8 4D
13

Output Control

Enable G

Data D

Output Q

5D 14 6D
17

74LS373 U1

L L L H

H H L X

H L X X

H L Q0 Logic Z

7D 18 8D

G
11 Enable

OC

1 Output Control

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What is a Multiplexer (MUX)?

A MUX is a digital switch that has multiple inputs (sources) and a single output (destination). The select lines determine which input is connected to the output. MUX Types
2-to-1 (1 select line) 4-to-1 (2 select lines) 8-to-1 (3 select lines) 16-to-1 (4 select lines)
Inputs
(sources)

Multiplexer
Block Diagram

MUX

2N

Output
(destination)

N Select Lines

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Typical Application of a MUX

Multiple Sources
MP3 Player Docking Station

Selector

Single Destination

D0 D1 D2 D3

MUX

Laptop Sound Card

Surround Sound System Digital Satellite B 0 0 1 A 0 1 0 1 Selected Source MP3 Laptop Satellite Cable TV

Digital Cable TV

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MULTIPLEXER (DATA SELECTOR)

A multiplexer is a logic circuit that accepts inputs from several different channels and feeds all of them into a single output channel in a sequential order It is a circuit that gates one of several inputs to a single output. It is multi-input single output combinational logic circuit. The input selected is controlled by a set of select (control) lines. MUX has n input lines and one output line. For selecting one input out of n inputs, a set of m select lines are required, where2 m = n. Normally, a active low strobe (enable) input (G) is incorporated.

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Block Diagram:
I0 I1 I2 I3 In-1

n:1 MUX

Strob / Enable
Sm-1 S2 S1 S0

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4-to-1 Multiplexer (MUX)

D0 D1 D2 D3

MUX

B 0 0 1 1

A 0 1 0 1

Y D0 D1 D2 D3
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4:1 Multiplexer:
Logic equation :

Y (S1 S0 I 0 S1S0 I1 S1 S0 I 2 S1S0 I3 ) G

Truth table:
Enable input G 0 0 0 0 1 Select inputs S1 0 0 1 1 X S0 0 1 0 1 X output Y I0 I1 I2 I3 0
I3 I2 I1

Select lines

S1

S0

Strobe or Enable G

I0

A 4:1 Multiplexer using NAND Gates

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Standard ICs are available for 2:1, 4:1, 8:1 and 16:1 multiplexers.

IC No.
74157 74158 74153 74352 74151A 74152 74150

Description
Quad 2:1 Multiplexer. Quad 2:1 Multiplexer. Dual 4:1 Multiplexer. Dual 4:1 Multiplexer. 8:1 Multiplexer. 8:1 Multiplexer. 16:1 Multiplexer.

Output
Same as input Inverted input. Same as input Inverted input. Inverted input. Inverted input. Inverted input.

Application of MUX: 1. Sequence generator. 2. Parallel to serial data converter . 3. Combinational logic device. 4. As a Multiplexer .

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8-to-1 MUX

Medium Scale Integration MUX

4-to-1 MUX
Inputs
Select Enable Output (Y)
(and inverted output)

8-to-1 MUX

16-to-1 MUX

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Multiplexer Tree:
8:1 MUX using two 4 :1 MUX Inputs
0 1 2 3

Output A 0 1 Y D0 D1

4:1 Y0 MUX
S0

G S1

C 0 0
Y

B 0 0

A B C
4 5 6 7 G S1 S0

4:1 Y1 MUX

0 0 1 1 1 1

1 1 0 0 1 1

0 1 0 1 0 1

D2 D3 D4 D5 D6 D7
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Alternative method:
0 1 2 3

4:1 Y0 MUX
S0 0 1 S1 S0 G

Logic 0

G S1

C
S0 Y

A B
4 5 6 7 G

Logic 0

4:1 Y1 MUX

Logic 0

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Full adder using multiplexer:

Implementation table for sum

Truth table:
Inputs A 0 0 B 0 0 Cin 0 1 Outputs Carry 0 0 Sum 0 1

D0

D1

D2

D3

A 0 1 1 0 A 1 0 0 1 A A A A
A

0
0 1 1 1 1
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1
1 0 0 1 1

0
1 0 1 0 1

0
1 0 1 1 1

1
0 1 0 0 1
Implementation table for Carry

D0

D1

D2

D3

A
A

0
0 0

1
1 1

1 1 A A

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Implementation of full adder using 4:1 MUX:

0 1 2 4:1 Y 3 MU X G S1 S0

SUM

A B Cin

Logic 0

Logic 0

0 1 2

S1 S0

Logic 1 Logic 0
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4:1 Y 3 MU X
G

CARRY

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Implementation of 4-variable logic equation using 8:1 MUX.

f ( A, B, C, D) m2,4,6,7,9,10,11,12,15
Solution:
1. 2. 3. 4. Write the truth table for the logic equation Connect inputs A, B and C to S2, S1, S0 select inputs respectively. Observe the relation between D and Y and prepared the reduction table. Implement this truth table using 8:1 MUX.

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Truth table
Inputs
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1

Output
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Y 0 0 1 0 1 0 1 1 0 1 1 1 1 0 0

Truth table after reduction logic

Inputs Output

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0

Y 0

D
1 0 1 0 1 1 D 1

D
D
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Logic 0
D

0 1 2 3 4 5

8 :1 Y

Logic1

Mux

Output

6 7

Logic 0

A B C

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f ( A, B, C, D) m(1,4,5,7,9,12,13)

ABC

D
0

D
1

D
0
1

0
2

1
3

I0 I1 I2

0
4

0
5 1 6
7

I3 I4 I5 I6

D D 0
1

8:1 MUX

0
8

1
9

0
10

1
11

0
12

0
13

I7

S2

S1

S0

1
14

1
15

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What is a Demultiplexer (DEMUX)?

A DEMUX is a digital switch with a single input (source) and a multiple outputs (destinations). The select lines determine which output the input is connected to. DEMUX Types
1-to-2 (1 select line) 1-to-4 (2 select lines) 1-to-8 (3 select lines) 1-to-16 (4 select lines)
Input
(source)

Demultiplexer
Block Diagram

DEMUX

2N

Outputs
(destinations)

N Select Lines

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Typical Application of a DEMUX

Single Source Selector Multiple Destinations
B/W Laser Printer Fax Machine

DEMUX

D0
D1 D2 D3

Color Inkjet Printer

B 0 0 1 1

A 0 1 0 1

Selected Destination B/W Laser Printer Fax Machine Color Inkjet Printer Pen Plotter Pen Plotter

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DEMULTIPLEXERS
Demultiplexer is a logic circuit with one input and many outputs. By applying proper control signal, we can steer (transfer) the input signal to one of the output lines. Fig shows block diagram of 1: n DEMUX. Din DEMUX The circuit has one input line n output lines and m select (control) lines. Where Sm -1 S2 S1 S0 m n=2
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Y0 Y1 Y2 Y3 Yn-1

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1-to-4 De-Multiplexer (DEMUX)

DEMUX
D0 D1 D2 D3 X

B 0 0 1 1

A 0 1 0 1

D0 D1 D2 D3 X 0 0 0 0 X 0 0 0 0 X 0 0 0 0 X
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1:4 (2-line to 4-line) Demultiplexer:

Logic diagram Block diagram
S1 S0
Strobe

Din

Y0 Y1
Din Y0

1:4 DEMUX Y 2
G S1 S0 Y3

Y1

Y2

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IC No. 74139 --------------------74155 --------------------74156

Description Dual 1:4 Demultiplexer (2-line to 4-line decoder) ----------------------------------do ----------------------------------do --------------------------------1: 8 Demultiplexer (3-line to 8-line decoder) --------------------------------1:16 Demultiplexer (4-line to 16-line decoder) ----------------------------------do--

Output Inverted input. --------------------------------1Y Inverted input. 2Y Same as input --------------------------------Open collector. 1Y Inverted input. 2Y Same as input --------------------------------Inverted input. --------------------------------Same as input.

--------------------74138 --------------------74154

--------------------74159

---------------------------------Same as input. Open collector.

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Medium Scale Integration DEMUX

1-to-4 DEMUX
Select Input
(inverted)

1-to-8 DEMUX

16-to-1 MUX

Outputs
(inverted)

Note : Most Medium Scale Integrated (MSI) DEMUXs , like the three shown, have outputs that are inverted. This is done because it requires few logic gates to implement DEMUXs with inverted outputs rather than no-inverted outputs. 46

Applications of DEMUX:
Data Distributor. Decoder To implement multi-output combinational logic expression.

Multiplexer and Demultiplexer in combination are used in Data transmission systems.

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Demultiplexer tree:
Enable
A1 B1 C1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

A B C D E (LSB)

(MSB)

D1

A2 B2 C2 D2

Enable

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16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

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Implementation of 1:8 DEMUX using two 1 : 4 DEMUX

Din
Din Y0 Y1 1:4 DEMUX Y 2 G S1 S0 Y3

A B C
S1 Din S0 Y4

Y5 1:4 DEMUX Y 6 G Y7

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The multi-output combinational circuit using DEMUX and some additional logic gates

Example: Implement the following multi-output combinational circuit using 4 to 16 lines DEMUX. F1 = m (0, 3, 5, 10) F2 = m (0, 2, 4, 10) F3 = m (2, 4, 11, 15) standard SOP form

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D in (To Logic 1)

Binary Inputs

Enable (To Logic 0)

0 1 2 3 4 A (MSB) 5 6 B 7 C 8 9 D (LSB) 10 11 12 13 14 15

N1

F1

N2

F2

N3

F3

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F1 = m (0, 3, 5, 10) F2 = m (0, 2, 4, 10) F3 = m (2, 4, 11, 15)

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Mux / Demux applications: All these six (mux, Demux, encoder, decoder, serial to parallel and || to serial convertors) devices are used in digital processing, telecommunications, instrumentation and computer architecture etc. And in a particular complete system they appear in pairs, like complex conjugates in maths. Frequency division, time division, wavelength division etc.

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