Concepts in VLSI Design

Presented by Niket Agrawal (MTech VLSI)

IIT Guwahati

What is a transistor (Digital Definition) A Switch!

VG S V T R on S D

An MOS Transistor
|VGS|

The NMOS Transistor

Threshol Voltage! Concept

S + VGS G D

n+

n+

n-channel p-substrate B

Depletion Region

Transistor in Linear
S VGS G n" & " L p#s$%strate B x VDS D n" ID

V(x)

MOS transistor an its %ias con itions

Transistor in Sat$ration
VGS G S n+
-

VDS > VGS - VT D

+

VGS - VT

n+

Pinch-off

C$rrent#Voltage 'elations Long#Channel De(ice

C$rrent#Voltage 'elations
6 x 10
-4

VGS= !" V

Resisti%e
4

Saturation
VGS= !# V

VDS = VGS - VT
VGS= $!" V

Quadratic Relationship

ID (A)

VGS= $!# V

0.5

1 V DS (V)

1.5

2.5

Velocit) Sat$ration
( Deep s$% *icron +ra)

n (m/s)

sat = 105
Constant velocity

Constant mobility (slope = )

c = 1.5

(V/m)

,erspecti(e
ID
Long-channel device VGS = VDD Short-channel device

V DSAT

VGS - V T

VDS

ID (ers$s V-S
6 5 4
ID (A)

x 10

-4

x 10 2.5

-4

&uadratic

linear
1.5
ID (A)

3 2 1 0 0

0.5

&uadratic
0.5 1
VGS(V)

1.5

2.5

0 0

0.5

1
VGS(V)

1.5

2.5

'ong (hannel

Short (hannel

A $nifie *o el for *an$al anal)sis

A ,MOS Transistor
0 x 10
-4

VGS = -$!#V -0.2 VGS = -$!"V -0.4

ID (A)

VGS = - !#V

-0.6

)ssu*e all %ariables negati%e+

-0.8

VGS = - !"V

-1 -2.5

-2

-1.5
VDS (V)

-1

-0.5

MOS Capacitances
G

CGS S

CGD D

CSB

CGB

CDB

The -ate Capacitance

,ol) silicon gate

So$rce n" xd Ld Top view xd

Drain n"

-ate#%$l/ o(erlap -ate o.i e

tox n" L Cross section n"

-ate Capacitance
G CGC S D S G CGC D S G CGC D

(ut-off

Resisti%e

Saturation

Most i*portant regions in igital esign! sat$ration an c$t#off

Diff$sion Capacitance
Channel-stop im plant N A1 Side wall W Source ND Bottom xj Side wall LS Channel Substrate NA

S$%#Threshol 'egion (MOS now a 01T)

10
-2

'inear
10
-4

10
ID (A)

-6

Quadratic

CD I D / I #e . n = $ + Cox

qVGS nkT

10

-8

10

-10

,-ponential VT
0.5 1
VGS (V)

10

-12

1.5

2.5

2a%rication

F r a great t ur thr ugh the I! "anu#acturing $r cess and its di##erent ste$s% check

htt$&''www(#ull"an(c "'se"ic nduct rs'se"ic nduct rs(ht"l

CMOS ,rocess at a -lance

Define active areas Etch and fill trenches

Implant well regions

Deposit and pattern polysilicon layer

Implant source and drain regions and substrate contacts

Create contact and via windows Deposit and pattern metal layers

In(erter La)o$t
VDD PMOS In Out NMOS

Metal Thic/ fiel o.i e p" n" n" p s$%strate p" n well p" n"

2a%rication Steps

Start with blank wa#er (ty$ically $)ty$e where NM*S is created) First ste$ will be t # r" the n)well (where PM*S w uld reside)

! +er wa#er with $r tecti+e layer # Si*, ( -ide) .e" +e -ide layer where n)well sh uld be built I"$lant r di##use n d $ants int e-$ sed wa#er t # r" n)well Stri$ ## Si*,

p s$%strate

O.i ation

Gr w Si*, n t $ # Si wa#er
/00

1 2,00 ! with 3,* r *, in -idati n #urnace

SiO 3

p s$%strate

,hotoresist

Ph t resist Ph t resist is a light)sensiti+e rganic $ ly"er Pr $erty changes where e-$ sed t light Tw ty$es # $h t resists ($ siti+e r negati+e) P siti+e resists can be re" +ed i# e-$ sed t 4V light Negati+e resists cann t be re" +ed i# e-$ sed t 4V light
,hotoresist SiO 3

p s$%strate

Lithograph)

5-$ se $h t resist t 4ltra)+i late (4V) light thr ugh the n)well "ask Stri$ ## e-$ sed $h t resist with che"icals

,hotoresist SiO 3

p s$%strate

+tch

5tch -ide with hydr #lu ric acid (3F) *nly attacks -ide where resist has been e-$ sed N)well $attern is trans#erred #r " the "ask t silic n)di) -ide sur#ace6 creates an $ening t the silic n sur#ace

,hotoresist SiO 3

p s$%strate

Strip ,hotoresist

Stri$ ## re"aining $h t resist

4se

"i-ture # acids called $iranah etch

Necessary s resist d esn7t "elt in ne-t ste$

SiO 3

p s$%strate

N#well

N)well is # r"ed with di##usi n r i n i"$lantati n 8i##usi n Place wa#er in #urnace with arsenic)rich gas 3eat until As at "s di##use int e-$ sed Si I n I"$lanatati n 9last wa#er with bea" # As i ns I ns bl cked by Si*,% nly enter e-$ sed Si Si*, shields ( r "asks) areas which re"ain $)ty$e
SiO 3 n well

Strip O.i e

Stri$ ## the re"aining -ide using 3F Subse:uent ste$s in+ l+e si"ilar series # ste$s

n well p s$%strate

,ol) silicon (self#aligne gate technolog))

8e$ sit +ery thin layer # gate -ide ; ,0 < (=)> at "ic layers) !he"ical Va$ r 8e$ siti n (!V8) # silic n layer Place wa#er in #urnace with Silane gas (Si3?) F r"s "any s"all crystals called $ lysilic n 3ea+ily d $ed t be g d c nduct r
,ol)silicon Thin gate o.i e n well

p s$%strate

Self#Aligne ,rocess

4se gate) -ide'$ ly silic n and "asking t e-$ se where n@ d $ants sh uld be di##used r i"$lanted N)di##usi n # r"s nM*S s urce% drain% and n)well c ntact

p s$%strate

n well

N# iff$sion4i*plantation

Pattern -ide and # r" n@ regi ns Self-aligned process where gate bl cks n) d $ants P lysilic n is better than "etal # r sel#)aligned gates because it d esn7t "elt during later $r cessing

n" Diff$sion

p s$%strate

n well

N# iff$sion4i*plantation cont5

3ist rically d $ants were di##used 4sually high energy i n)i"$lantati n used t day 9ut n@ regi ns are still called di##usi n

n"

n" p s$%strate n well

n"

,#Diff$sion4i*plantation

Si"ilar set # ste$s # r" $@ Adi##usi nB regi ns # r PM*S s urce and drain and substrate c ntact

p" Diff$sion

p"

n"

n" p s$%strate

p" n well

p"

n"

Contacts

N w we need t wire t gether the de+ices ! +er chi$ with thick #ield -ide (F*) 5tch -ide where c ntact cuts are needed
Contact

Thic/ fiel o.i e p" n" n" p s$%strate p" n well p" n"

Metali6ation

S$utter n alu"inu" +er wh le wa#er G ld is used in newer techn l gy Pattern t re" +e e-cess "etal% lea+ing wires

Metal

Metal Thic/ fiel o.i e p" n" n" p s$%strate p" n well p" n"

CMOS INV+'T+'
VDD PMOS In Out NMOS
Rn V out V DD V DD Rp V out

V in 5 V DD

V in 5 0

CMOS In(erter VTC

Vout !" 012S off P12S res 012S s at P12S res 012S sat P12S sat 012S res P12S sat

VDD PMOS In Out NMOS

012S res P12S off !" Vin

#!"

$!"

# !"

$ !"

CMOS In(erter ,ropagation Dela)

VDD

tpHL = f(

on!CL" onCL

= #!$%
Vout CL Ron
7

Vo$t VDD

ln(859)

859 85:;

Vin = V DD 'onCL
t

Transient 'esponse
3 2.5 2 1.5 1 0.5 0 -0.5 0

3
tp = 0.69 CL (Reqn+Reqp)/2
tp'4 tp4'

out

(V)

0.5

1 t (sec)

1.5

2 x 10

2.5
-10

Design for ,erfor*ance

Cee$ ca$acitances s"all Increase transist r siDes

watch

ut # r sel#)l adingE

Increase V88 (FFF)

Dela) as a f$nction of VDD

5.5 5 4.5 4

t (normalized)

3.5 3 2.5 2 1.5 1 0.8

1.2

1.4

1.6

1.8

2.2

2.4

DD

(V)

Dela) as a f$nction of De(ice Si6ing

3.8 3.6 3.4 3.2 t (sec) 3 2.8 2.6 2.4 2.2 2 2 4 6 8 S 10 12 14 x 10
-11

5for fi-ed load6

Self-loading effect7 8ntrinsic capacitances do*inate

Where Does ,ower -o in CMOS<

& Dynamic 'ower Consumption
Charging and Discharging Capacitors

& (hort Circuit Currents

(hort Circuit 'ath between (upply ails during (witching

& Lea)age
Lea)ing diodes and transistors

D)na*ic ,ower Dissipation

Vdd

Vin CL

Vo!t

Energy/transition = CL * Vdd2 Po er = Energy/transition * f = CL * Vdd2 * f

Short Circuit Currents

Vd d

Vin CL

Vo!t

0.15

IVDD (mA)

0.10

0.05

0.0

1.0

2.0 3.0 Vin (V)

4.0

5.0

Leakage
Vd d

Vo!t

Drain Junction Leakage Sub-Threshold Current

S$%#threshol c$rrent one of *ost co*pelling iss$es Sub-Threshold Current Dominant Factor in low#energ) circ$it esign!

,rinciples for ,ower 'e $ction

Pri"e ch ice& .educe + ltageE

.ecent

years ha+e seen an accelerati n in su$$ly + ltage reducti n 8esign at +ery l w + ltages still $en :uesti n (0(= G 0(/ V by ,020E)

.educe switching acti+ity .educe $hysical ca$acitance

-oals of Technolog) Scaling

Make things chea$er&

Hant

t sell " re #uncti ns (transist rs) $er chi$ # r the sa"e " ney 9uild sa"e $r ducts chea$er% sell the sa"e $art # r less " ney Price # a transist r has t be reduced

9ut als want t be #aster% s"aller% l wer $ wer

Static CMOS Circ$it

"t e#ery point in ti$e (e%&ept d!ring t'e s it&'ing transients) ea&' gate o!tp!t is &onne&ted to eit'er VDD or Vss #ia a (o )resisti#e pat'. *'e o!tp!ts o+ t'e gates ass!$e at a(( ti$es t'e #a(!e o+ t'e ,oo(ean +!n&tion- i$p(e$ented .y t'e &ir&!it (ignoring- on&e again- t'e transient e++e&ts d!ring s it&'ing periods). *'is is in &ontrast to t'e dynamic &ir&!it &(ass- 'i&' re(ies on te$porary storage o+ signa( #a(!es on t'e &apa&itan&e o+ 'ig' i$pedan&e &ir&!it nodes.

Static Co*ple*entar) CMOS

VDD In7 In3 InN In7 In3 InN ,DN ,MOS onl) 2(In7=In3=>InN)

,?N

,?N an ,DN are $al logic networ/s

9 9

NMOS onl)

Threshol Drops
,?N VDD
S

VDD VDD 8 VDD CL V-S

D

8 VDD # VTn CL VDD @VTp@

,DN VDD
D

VDD 8 CL

V-S

CL

+.a*ple -ate! NAND

Co*ple. CMOS -ate

0 A C D O?T A D " A B (0 " C) A D 0 C

CMOS ,roperties

Full rail)t )rail swing6 high n ise "argins L gic le+els n t de$endent u$ n the relati+e de+ice siDes6 rati less Always a $ath t Vdd r Gnd in steady state6 l w ut$ut i"$edance 5-tre"ely high in$ut resistance6 nearly Der steady)state in$ut current N direct $ath steady state between $ wer and gr und6 n static $ wer dissi$ati n Pr $agati n delay #uncti n # l ad ca$acitance and resistance # transist rs

Dela) Depen ence on Inp$t ,atterns

3 2.5 2

AA0A78 AA7 8= 0A7 AA7= 0A78

Input Data Pattern AI9I02 AI2% 9I02 AI 02% 9I2 AI9I20 AI2% 9I20 AI 20% 9I2

Delay (psec) => =? =2 ?J K0 K2

Voltage CVD

1.5 1

0.5 0

-0.5

100

200

300

400

ti*e CpsD

2ast Co*ple. -ates! Design TechniE$e 7

Transist r siDing
as

l ng as #an) ut ca$acitance d "inates

Pr gressi+e siDing
InN
MN

CL

Distri%$te 'C line M7 F M3 F M: F > F MN (the fet closest to the o$tp$t is the s*allest) Can re $ce ela) %) *ore than 38GH ecreasing gains as technolog) shrin/s

In: In3 In7

M: M3 M7

C: C3 C7

2ast Co*ple. -ates! Design TechniE$e 3

Transist r rdering
critical path In: 7 M: In3 7 M3 In7 M7 87 charge CL C3 charge C7 charge critical path 87 In7 M: In3 7 M3 In: 7 M7 charge CL C3 ischarge C7 ischarge

ela) eter*ine %) ti*e to ischarge CL= C7 an C3

ela) eter*ine %) ti*e to ischarge CL

S$**ar)

It was a big talk At last it #inished N w I Hant t enL y Sunday