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Outline
Bus organization
Address/Data Bus
Control Bus
Bus Organization
8085 CPU
U1 36 1 2 5 6 9 8 7 10 11 29 33 39 35 RST-IN X1 X2 SID TRA P RST 5.5 RST 6.5 RST 7.5 INTR INTA S0 S1 HOLD REA DY 8085 A LE WR RD IO/M RST-OT CLKO SOD HLDA A D0 A D1 A D2 A D3 A D4 A D5 A D6 A D7 A8 A9 A 10 A 11 A 12 A 13 A 14 A 15 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 30 31 32 34 3 37 4 38
8085
Data Bus
Control Bus
Memory
Interface
What is an Interface?
an interface is a concept that refers to a point of
interaction between components, and is applicable at the level of both hardware and software.
This allows a component, (such as a graphics card or
an Internet browser), to function independently while using interfaces to communicate with other components via an input/output system and an associated protocol.
8085
ALE
IO/ M / S1 / S 2 RD
WR Control Bus
Higher-order Address
Lower-order Address
A15 A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Data Bus
Address/Data Bus
unidirectinal bus.
It carries most significant 8-bits of a 16-bit
is not completed.
Question
How the processor knows the Lower Order bits is for Address or Data?
Demultiplexing (DEMUX)
Demultiplexing
A hardware register provided by the system designer to save the contents of the data bus and low order address lines. 8085 microprocessor commonly uses latch to demultiplex the address and data bus. The most widely used latch for demultiplexing is 74LS373 IC. separation of address/data bus AD0-AD7 into address bus A7A0 and data bus D7D0. The data bus and low order address lines are multiplexed in order to save pin count.
Multiplexing
A method by which multiple digital data streams are combined into one signal over a shared medium.
Lower order address bus & Data bus are on the 8085 microprocessor multiplexed on same lines i.e. AD0 to AD7 and A8 to A15.
74LS373
Control Bus
I/O devices
Enable system to interact with the world The MPU views the I/O device registers just like memory that can be accessed over the bus. However, I/O registers are connected to external wires, device control logic, etc. The MPU accepts binary data as input from devices (keyboards and Analog To Digital (A/D) converters) and sends the data to output devices (LEDs and printer)
Address Decoders
Memory Chip
k data input lines
n address lines read write Memory Chip select 2n words k bits per word k data output lines
11 10
01 00 Memory 2
01
00
Memory 1
011
010 001 000
11
111
110 101 100
10 01
00
CS
00
A2
CS
Memory 1
Memory 2
decoders.
Using M-Line to N-Line Decoder - Use existing general decoders such as 74LS138, 74LS154 and etc.
Using PAL or FPGA - Using Programmable logic array devices such as PAL22V10 , PAL16L8 or Field Programmable Gate
Example
ROM & RAM Size
ROM size 8K x 8 bit
Memory Map
0000H 1FFFH 2000H 0000H
3FFFH 4000H
ROM RAM
Not Used
RAM ROM
Not Used
OR
FFFFH
FFFFH
Address Decoding
ROM RAM A15..A12 0000 0001 0010 0011 A11..A8 A7..A4 0000 0000 1111 1111 0000 0000 1111 1111 A3..A0 0000 1111 0000 1111
Note:
ROM CS
RAM CS
ROM CS RAM CS
A 0 1 0 1 0 1 0 1 Y0 0 1 1 1 1 1 1 1 Y1 1 0 1 1 1 1 1 1 OUTPUT Y2 Y3 Y4 Y5 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 Y6 1 1 1 1 1 1 0 1 Y7 1 1 1 1 1 1 1 0
C 0 0 0 0 1 1 1 1
INPUT B 0 0 1 1 0 0 1 1
X X X 0 0 0 0 1 1 1 1
X X X 0 0 1 1 0 0 1 1
X X X 0 1 0 1 0 1 0 1
0 1 1 1 1 1 1 1 1 1 1
X 1 0 0 0 0 0 0 0 0 0
X X 1 0 0 0 0 0 0 0 0
1 1 1 0 1 1 1 1 1 1 1
1 1 1 1 0 1 1 1 1 1 1
1 1 1 1 1 0 1 1 1 1 1
OUTPUT Y3 Y4 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1
Y5 Y6 Y7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0
decoding techniques
Exhaustive Decoding
In this type of scheme all the 16 bits of the
8085 address bus are used to select a particular location in memory chip. Advantages: Complete Address Utilization Ease in Future Expansion No Bus Contention, as all addresses are unique. Disadvantages Increased hardware and cost. Speed is less due to increased delay.
Partial Decoding
In this scheme minimum number of address lines are used as required to select a memory location in chip. Advantages:
Simple, Cheap and Fast. Disadvantages: Unutilized space & fold back (multiple mapping). Bus Contention. Difficult future expansion.
I/O Mapping
between the microprocessor and the outside world. This can be done in groups of 8 bits using the entire data bus. This is called parallel I/O. The other method is serial I/O where one bit is transferred at a time using the SID and SOD pins on the Microprocessor.
I/O devices in parallel data transfer mode: Memory Mapped I/O I/O Mapped I/O
location. They are assigned a 16-bit address within the address range of the 8085. The exchange of data with these devices follows the transfer of data with memory. The user uses the same instructions used for memory.
Hardware. Can address 28=256 locations. Whole memory address space is available.
used. Memory control signals are used. Arithmetic and logic operations can be performed on data. Data transfer b/w register and IO.
used like IN, OUT. Special control signals are used. Arithmetic and logic operations can not be performed on data. Data transfer b/w accumulator and IO.
continue appearing on the output device for a long period of time. Given that the data will only be present on the data lines for a very short period (microseconds), it has to be latched externally.
enabled when the ports address is present on the address bus, the IO/M signal is set high and WR is set low.
The resulting signal would be active when
the output device is being accessed by the microprocessor. Decoding the address bus (for memorymapped devices) follows the same techniques discussed in interfacing memory.
interfacing of output devices. The address lines are decoded to generate a signal that is active when the particular port is being accessed. An IO/RD signal is generated by combining the IO/M and the RD signals from the microprocessor.
input device to the data bus. The control (Enable) for these buffers is connected to the result of combining the address signal and the signal IO/RD.