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EMT 248:

Design 8085 Microprocessor System


Semester II 2013/14
School of Microelectronic Engineering Universiti Malaysia Perlis

Outline
Bus organization

Address/Data Bus
Control Bus

Memory and I/O


Address Decoders I/O Mapping

Bus Organization

8085 CPU
U1 36 1 2 5 6 9 8 7 10 11 29 33 39 35 RST-IN X1 X2 SID TRA P RST 5.5 RST 6.5 RST 7.5 INTR INTA S0 S1 HOLD REA DY 8085 A LE WR RD IO/M RST-OT CLKO SOD HLDA A D0 A D1 A D2 A D3 A D4 A D5 A D6 A D7 A8 A9 A 10 A 11 A 12 A 13 A 14 A 15 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 30 31 32 34 3 37 4 38

8085 Microprocessor System Block Diagram

Example Block Diagram


Address Bus

8085

Data Bus
Control Bus

Memory

Interface

What is an Interface?
an interface is a concept that refers to a point of

interaction between components, and is applicable at the level of both hardware and software.
This allows a component, (such as a graphics card or

an Internet browser), to function independently while using interfaces to communicate with other components via an input/output system and an associated protocol.

8085 Interfacing Pins


Higher Address Bus Lower Address/Data Bus

A15 A8 AD7 AD0

8085

ALE
IO/ M / S1 / S 2 RD

WR Control Bus

The 8085 Bus Structure


Consists of 16 address lines: A0 A15 Operates in unidirectional mode: The address bits are always sent from the MPU to peripheral devices, not reverse. 16 address lines are capable of addressing a total of 216 = 65,536 (64k) memory locations.

Address locations: 0000 (hex) FFFF (hex)

The 8085 Bus Structure


Data Bus Consists of 8 data lines: D0 D7 Operates in bidirectional mode: The data bits are sent from the MPU to peripheral devices, as well as from the peripheral devices to the MPU.

Higher-order Address

Lower-order Address

A15 A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

Data Bus

The 8085 Bus Structure


Control Bus Comprised of various signal lines that carry synchronization signals The MPU use such lines to perform the third function: providing timing signals A group of signal includes: two control signals (RD/ and WR/) Three status signals ( IO/ M, S1, S 2 ) to identify the nature of the operation, One special signal (ALE) to indicate the beginning of the operation.

Address/Data Bus

Higher Order Address Bus


The higher order address bus is a

unidirectinal bus.
It carries most significant 8-bits of a 16-bit

address of memory or I/O device.


Address remains on lines as long operation

is not completed.

Lower Order Address/Data Bus


This bus is bidirectional and works on

time division multiplexing between address and data.


During first clock cycle, it serves as a least significant 8-bits of memory/ IO address. For second and third clock cycles it acts as data bus and carries data.

Question
How the processor knows the Lower Order bits is for Address or Data?

Demultiplexing (DEMUX)

Demultiplexing
A hardware register provided by the system designer to save the contents of the data bus and low order address lines. 8085 microprocessor commonly uses latch to demultiplex the address and data bus. The most widely used latch for demultiplexing is 74LS373 IC. separation of address/data bus AD0-AD7 into address bus A7A0 and data bus D7D0. The data bus and low order address lines are multiplexed in order to save pin count.

How the Latch / Demultiplexer is Function?


1st clock cycle, lower address is transferred on AD0 AD7. ALE is high and latch is enabled. Address available at A0 A7. 2nd and 3rd clock cycle ALE goes low and latch is disabled. ADoAD7 will act as D0D7.

Multiplexing
A method by which multiple digital data streams are combined into one signal over a shared medium.
Lower order address bus & Data bus are on the 8085 microprocessor multiplexed on same lines i.e. AD0 to AD7 and A8 to A15.

74LS373

Control Bus

8085 Machine Cycle Status and Control Signal

8085 Machine Cycle Status and Control Signal

Memory and I/O

Memory and I/O Memory


Where instructions (programs) and data are stored Organized in arrays of locations (addresses), each storing one byte (8 bits) in general A read operation to a particular location always returns the last value stored in that location. The memory is made up of semiconductor material used to store the programs and data. The types of memory is, Primary or main memory - RAM and ROM storing a program temporarily (commonly called loading) and executing a program. speed of this type of memory should be fast.

Memory and I/O


Secondary memory - Floppy, Hard Disk and CD-ROM used for bulk storage of data and information Slower and Sequential Access Nature. non-volatile nature.

I/O devices
Enable system to interact with the world The MPU views the I/O device registers just like memory that can be accessed over the bus. However, I/O registers are connected to external wires, device control logic, etc. The MPU accepts binary data as input from devices (keyboards and Analog To Digital (A/D) converters) and sends the data to output devices (LEDs and printer)

Address Decoders

Memory Chip
k data input lines
n address lines read write Memory Chip select 2n words k bits per word k data output lines

Interface with two memory chips


A1 A0 11 10

11 10
01 00 Memory 2

01
00

Memory 1

Interface with two memory chips


A1 A0
11 10 01

011
010 001 000

11

111
110 101 100

10 01
00
CS

00
A2
CS

Memory 1

Memory 2

Interface with Multiple Chips


In case of multiple chips, simple

circuit like NOT gate will not work.


In this case normally decoder

circuits like 3-to-8 decoder circuit 74LS138 are used.


These circuit are called address

decoders.

Interface with Multiple Chips


Using random logic - Using logic gates such as AND, OR, NOT and etc.

Using M-Line to N-Line Decoder - Use existing general decoders such as 74LS138, 74LS154 and etc.
Using PAL or FPGA - Using Programmable logic array devices such as PAL22V10 , PAL16L8 or Field Programmable Gate

Array, i.e. XILINK.

Example
ROM & RAM Size
ROM size 8K x 8 bit

13 bit address line A0 - A12 213 = 8192 (0000H - 1FFFH)


RAM size 8K x 8 bit

13 bit address line A0 - A12 213 = 8192 (0000H - 1FFFH)

Memory Map
0000H 1FFFH 2000H 0000H

3FFFH 4000H

ROM RAM
Not Used

1FFFH 2000H 3FFFH 4000H

RAM ROM
Not Used

OR
FFFFH

FFFFH

Address Decoding
ROM RAM A15..A12 0000 0001 0010 0011 A11..A8 A7..A4 0000 0000 1111 1111 0000 0000 1111 1111 A3..A0 0000 1111 0000 1111

Note:

ROM A13 = 0 , RAM A13 = 1 Memory access, signal IO/M = 0

Memory Decoding Using Random Logic


OR
A15 A14 A13

ROM CS

RAM CS

Memory Decoding Using 3 to 8 Decoder (74LS138)


A13 A14 A15
1 2 3 6 4 5 U5 A B C G1 G2A G2B 74LS138 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 15 14 13 12 11 10 9 7

ROM CS RAM CS
A 0 1 0 1 0 1 0 1 Y0 0 1 1 1 1 1 1 1 Y1 1 0 1 1 1 1 1 1 OUTPUT Y2 Y3 Y4 Y5 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 Y6 1 1 1 1 1 1 0 1 Y7 1 1 1 1 1 1 1 0

+5V IO/M GND

C 0 0 0 0 1 1 1 1

INPUT B 0 0 1 1 0 0 1 1

Truth Table 74LS138


INPUT
C B A G1 G2A G2B Y0 Y1 Y2

X X X 0 0 0 0 1 1 1 1

X X X 0 0 1 1 0 0 1 1

X X X 0 1 0 1 0 1 0 1

0 1 1 1 1 1 1 1 1 1 1

X 1 0 0 0 0 0 0 0 0 0

X X 1 0 0 0 0 0 0 0 0

1 1 1 0 1 1 1 1 1 1 1

1 1 1 1 0 1 1 1 1 1 1

1 1 1 1 1 0 1 1 1 1 1

OUTPUT Y3 Y4 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1

Y5 Y6 Y7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0

Types of Address Decoding


There are two types of address

decoding techniques

Exhaustive Decoding Partial Decoding

Exhaustive Decoding
In this type of scheme all the 16 bits of the

8085 address bus are used to select a particular location in memory chip. Advantages: Complete Address Utilization Ease in Future Expansion No Bus Contention, as all addresses are unique. Disadvantages Increased hardware and cost. Speed is less due to increased delay.

Partial Decoding
In this scheme minimum number of address lines are used as required to select a memory location in chip. Advantages:

Simple, Cheap and Fast. Disadvantages: Unutilized space & fold back (multiple mapping). Bus Contention. Difficult future expansion.

I/O Mapping

Interfacing I/O Devices


Using I/O devices data can be transferred

between the microprocessor and the outside world. This can be done in groups of 8 bits using the entire data bus. This is called parallel I/O. The other method is serial I/O where one bit is transferred at a time using the SID and SOD pins on the Microprocessor.

Types of Parallel Interface


There are two ways to interface 8085 with

I/O devices in parallel data transfer mode: Memory Mapped I/O I/O Mapped I/O

Memory Mapped I/O


It considers them like any other memory

location. They are assigned a 16-bit address within the address range of the 8085. The exchange of data with these devices follows the transfer of data with memory. The user uses the same instructions used for memory.

I/O Mapped I/O


It treats them separately from memory. I/O devices are assigned a port number within the 8-bit address range of 00H to FFH. The user in this case would access these devices using the IN and OUT instructions only.

I/O Mapped I/O


Memory Mapped I/O
I/O is treated as memory. 16-bit addressing. More Decoder Hardware. Can address 216=64k

I/O Mapped I/O


I/O is treated I/O. 8- bit addressing. Less Decoder

locations. Less memory is available

Hardware. Can address 28=256 locations. Whole memory address space is available.

I/O mapped I/O Vs Memory Mapped I/O


Memory Mapped I/O
Memory Instructions are

I/O Mapped I/O


Special Instructions are

used. Memory control signals are used. Arithmetic and logic operations can be performed on data. Data transfer b/w register and IO.

used like IN, OUT. Special control signals are used. Arithmetic and logic operations can not be performed on data. Data transfer b/w accumulator and IO.

The interfacing of output devices


Output devices are usually slow. Also, the output is usually expected to

continue appearing on the output device for a long period of time. Given that the data will only be present on the data lines for a very short period (microseconds), it has to be latched externally.

The interfacing of output devices


To do this, the external latch should be

enabled when the ports address is present on the address bus, the IO/M signal is set high and WR is set low.
The resulting signal would be active when

the output device is being accessed by the microprocessor. Decoding the address bus (for memorymapped devices) follows the same techniques discussed in interfacing memory.

The interfacing of Input devices


The basic concepts are similar to

interfacing of output devices. The address lines are decoded to generate a signal that is active when the particular port is being accessed. An IO/RD signal is generated by combining the IO/M and the RD signals from the microprocessor.

The interfacing of Input devices


A tri-state buffer is used to connect the

input device to the data bus. The control (Enable) for these buffers is connected to the result of combining the address signal and the signal IO/RD.

Thank you Q&A

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