Memory Controllers

Memory Controllers

Motivation
Many memory controllers have as features:
Multiple ports Single port memory devices SRAM, DRAM, or SDRAM or technology

Have seen failures in multiple flight systems

Circuit design errors Risky, complex architectural decisions

Memory Controllers

Background

SRAM Technology Overview

Memory Controllers

Some SDRAM Features

Synchronous Timing
Signal generation much simpler than DRAM

Complex devices with state machines, pipelines, refresh modes, power states, etc. Like DRAM, startup sequence required

Memory Controllers

Control Signals Sampled Synchronously

Block Diagram
Micron, 64 Mbit
4 Banks

Mode Register

Memory Controllers

Block Diagram
Control Signals Sampled Synchronously

Micron, 64 Mbit
CKE CLK CS* WE* CAS* RAS*

Mode Register
Memory Controllers 6

Control Signal Interpretation

Function COMMAND INHIBIT NOP LOAD MODE REGISTER AUTO/SELF REFRESH PRECHARGE ACTIVE (SEL BANK/ROW) WRITE READ BURST TERMINATE CS* H H L L L L L L L RAS* X X L L L L H H H CAS* X X L L H H L L H WE* X X L H L H L H L

Memory Controllers

Example Read w/ Auto Precharge

CAS Latency=2; Burst Length=4

Memory Controllers

Load Mode Register Command

Address Used As Operation Code

A2:A0
A3 A6:A4 A8:A7 A9

Burst Length
Burst Type {Sequential, Interleaved} CAS Latency Operation Mode Write Burst Mode

A11:A10 Reserved

Memory Controllers

Load Mode Register Command

Examination of Some Fields - Burst Length
A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Memory Controllers

BURST LENGTH M3=0 M3=1 1 1 2 2 4 4 8 8 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED FULL PAGE RESERVED
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Load Mode Register Command

Examination of Some Fields - CAS Latency
A6 A5 A4 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Memory Controllers 11

CAS LATENCY RESERVED RESERVED 2 3 RESERVED RESERVED RESERVED RESERVED

Load Mode Register Command

Examination of Some Fields - Op Mode
A8 A7
0 0 1 1 0 1 0 1

Operation Mode
Standard Operation RESERVED RESERVED RESERVED

Memory Controllers

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State Diagram, Simplified [3]

Hitachi 256M SDRAM
Lockup states?
Self Refresh
Load Mode Reg

Idle

Auto Refresh
Idle Power Down

Read/ Write

Power On
Memory Controllers

Precharge
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Mode Register and Device State

Special Considerations
Mode Register likely SEU Soft
Test data supports this

RESERVED states in Mode Register

May be able to load invalid state May require power cycle May result in damage to device

Toggling N/C Pins

May require power cycle to recover May result in damage to device

Poor Signal Integrity or Power/Ground Noise

Memory Controllers

May upset Mode Register: put into a RESERVED state

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What Happens with Heavy Ions?

Memory Controllers

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Heavy Ion SEUs, 128 Mbit

Samsung [2]
SEE Event
Cross-section (cm2/device)

SEL

KM44S32030B

LET (MeV-cm2/mg)
Memory Controllers 16

Heavy Ion SEUs, 256 Mbit [2]

Samsung
Multiple bit upsets seen LETTH is around 1 MeV-cm2/mg

Hitachi
Multiple bit upsets seen LETTH is around 1 MeV-cm2/mg

Memory Controllers

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Heavy Ion: Stuck Bits

Reference [1] reports 30 stuck bits on one 128 Mb device, after exposure to a large fluence. Fewer stuck bits observed after being annealed at room temperature, unbiased for one week. Reference [2] reports stuck bits for the 256M Samsung devices. The small number of stuck bits annealed within a few weeks in an unbiased condition.
Memory Controllers 18

Loss of Functionality and other Unusual Events

Radiation Signal Integrity

Memory Controllers

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Large Event - Samsung [1]

Most or all bits wrong were seen a few times for the 128 Mbit Samsung device; it was not seen for the 64 Mbit Samsung SDRAM.
Memory Controllers 20

Loss of Functionality - Early Data

256M Samsung [2]
Often, reset (power cycle) is needed to recover from SEFI conditions. [2] Large multiple bit errors (> 100 bits) making an oval patch in the memory Multiple-bit errors over many consecutive address locations Events above may have an increase of about 10 mA in supply current.

256 Hitachi [2]

Also seen. Anomalous Currents Ranged from 0.5 to 145 mA [3]
Memory Controllers 21

Loss of Functionality [3]

Hyundai 256M (Auto Refresh Operation)
10-3

Cross-section (cm2/device)

10-4

10-5

10-6

10-7

LET (MeV-cm2/mg)
Memory Controllers 22

Loss of Functionality
Additional Issues
Refreshing MODE Register
Will restore functionality in some cases But not all!

Different ways of operating SDRAM can result in different affects from radiation. See Reference [3] for details.

Memory Controllers

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Loss of Functionality - A Sample

See Ref. 3 for Detailed Data
Self-Refresh Operation: Power Cycle Required
LET HIT256M HYND256M SAM128M SAM256M

4.1 12 28

X X

N/A N/A X

X X

N/A X X

No problem N/A Data Not Available X Power Cycle Required

Memory Controllers 24

Design FSM Controllers

Memory Controllers

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Data Flow
Producer Process Consumer Process

SDRAM

Memory Controllers

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One Flight Hardware Approach

Control Signals Shown
FPGA

Producer FSM

Arbitration

Consumer FSM
Arbitration between the FSMs complex, a small error was made, resulting in putting the SDRAM in an illegal state, potentially damaging it, and locking up the entire system.
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OR Gate

SDRAM
Memory Controllers

Another Flight Hardware Design

Control Signals Shown
Producer FSM
Arbitration

Consumer FSM
Arbitration between the FSMs complex, a small error was made, resulting in putting glitches into the SRAM, destroying the contents, and locking up the entire system.
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Tri-State Mux

SRAM
Memory Controllers

A Reliable Flight Hardware Topology

Control Signals Shown
Producer Consumer

Arbiter
Timer to refresh xRAM state

Controller FSM

xRAM
Memory Controllers 29

Some Recommendations for Memory Data Path

Stuck Bits
These are common place and can weaken EDAC
Stronger EDAC Map pages

May anneal over times

Multiple Bit Errors

Use EDAC as appropriate

Memory Controllers

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Some Recommendations for Memory Controllers

Control Register
Illegal configuration can lockup SDRAM
May be cleared by reloading; provide either automatic or commandable reload. May require power cycling. Support power cycling at either the subsystem or circuit level

Illegal configuration can damage SDRAM SDRAM control registers can not be read
Bummer.
Memory Controllers 31

Some Recommendations for Memory Controllers (cont'd)

Design a robust, correct arbiter Design a robust, correct, memory controller Do not mix the above two logic blocks

Memory Controllers

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