N.

Senthil Kumar,
M. Saravanan &
S. Jeevananthan
Oxford University Press 2013

ADVANCED MICROPROCESSORS
Oxford University Press 2013
ADVANCED MICROPROCESSORS
Architecture of Intel 80186, 80286, 80386, 80486 and
Pentium
The protected mode operation in 80286 to Pentium
microprocessors
Paging mechanism present in 80386 to Pentium
microprocessors
Integer and floating-point pipeline operation in Pentium
Different versions of Pentium microprocessor

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Introduction
After the release of 8086, Intel introduced 80186 which is a 16-bit processor
having architecture identical to that of 8086.
In addition, 80186 has more in-built hardware units such as three timers,
two DMA controllers, one interrupt controller, and peripheral and memory
select logic in it.
In 80286, Intel introduced protected mode addressing, also known as
protected virtual address mode (PVAM), which is an important milestone in
the development in the Intel X86 family.
80286 uses the numeric coprocessor 80287 for performing floating-point
operations.
After 80286, Intel released 80386, which is the Intels first 32-bit
microprocessor.
Most of the registers in 80386 are 32-bits wide, and the address bus and
data bus are also 32-bits wide.
80386 uses the numeric coprocessor 80387 for performing floating-point
operations.
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Introduction
After 80386, Intel released 80486, which is also a 32-bit
microprocessor.
Most of the registers in 80486 are 32-bits wide, and the address bus
and data bus are also 32-bits wide.
There is no need for any coprocessor in 80486 based systems due to
the inclusion of FPU in the 80486 chip itself.
The presence of cache memory within the 80486 chip reduces the
execution time of a program by 80486.
Pentium has 8 Kbyte on-chip dual cache (8 Kbyte code cache and 8
Kbyte data cache), and on-chip FPU which uses an eight stage
floating point pipeline.
Pentium has 64-bit data bus and 32-bit address bus.
The architecture and salient features of the processors, from 80186
to Pentium are explained below one by one.


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80186 Architecture
The 80186 processor includes the following subsystems:
A Clock generator
A programmable interrupt controller
Three 16-bit programmable timers/counters
Two programmable DMA controllers
Chip select unit
Programmable control registers
Bus interface unit
Six-byte prefetch queue
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Functional block diagram of
80186 (Intel Corp.)
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Description
The two channel DMA unit of the 80186 performs transfers to or from any
combination of I/O space and memory space in either byte or word units.
Each DMA channel maintains independent source and destination pointers
which are used to access the source and destination of transferred data.
The 80186 timer unit contains three independent 16-bit timer/counters. Two of
these timers can be used to count external events, to provide waveforms derived
from either the CPU or an external clock, or to interrupt the CPU after a specified
number of timer events.
The third timer counts only CPU clock cycles and can be used to interrupt the
CPU after a programmable number of CPU clocks, to give a count pulse to either
or both of the other two timers after a programmable number of CPU clocks, or
to give a DMA request pulse to the integrated DMA unit after a programmable
number of CPU clock cycles.

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Description
The 80186 interrupt controller processes the interrupt requests
from all internal and external sources.
It can be directly cascaded as the master to two external 8259As
(programmable interrupt controllers).
The 80186 integrated chip select logic can be used to enable
memory or peripheral devices.
Six output lines from the integrated chip select logic are used for
memory addressing and seven output lines are used for peripheral
device addressing.
The integrated peripheral and chip select circuitry is controlled by
sets of 16-bit registers accessed using standard input, output, and
memory access instructions.
These peripheral control registers are all located within a 256 byte
block that can be placed in either memory or I/O space
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Instruction set of 80186
The 80186 includes all of the instructions of the 8086.
In addition, few new instructions such as BOUND,
ENTER, LEAVE, INS, OUTS are introduced in 80186.
Some of the 8086 instructions have been given
additional features such as: PUSH an immediate value
into stack, PUSHA (PUSH all the registers in to stack in
the order AX,CX,DX,BX,SP,BP,SI,DI), POPA (POP all the
registers from stack in the order DI,SI,BP,SP,BX,DX,CX,AX),
IMUL by an immediate value, and Shifts/rotates a
register or memory content by an immediate value.

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80286 Architecture
The Execution Unit (EU) which includes the ALU, general
registers (which are same as in 8086 and 80186) and the
control unit (CU).
The execution unit uses its 16-bit ALU to execute instructions
that is received from the instruction unit.
The address unit (AU) which includes the segment registers
(which are same as in 8086 and 80186), an offset adder and a
physical address adder.
The address unit in 80286 computes the physical addresses
that will be sent out to memory or I/O by the bus unit.

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80286 Architecture
The bus unit (BU) which includes the address latches and
transceivers, bus interface and control circuitry, instruction
prefetcher, and a 6-byte instruction queue.
The bus unit performs all memory and I/O reads and writes,
prefetches instruction bytes and controls the transfer of data
to and from processor extension devices such as 80287.
The instruction unit (IU) which includes an instruction decoder
and a three decoded instructions queue.
The instruction unit fully decodes upto three prefetched
instructions and holds them in a queue, where the execution
unit can access them.


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80286 Architecture
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Register organization and real &
protected addressing in 80286
The 80286 register set is the same as that of an 8086 except for the addition of a 16-
bit Machine Status Word (MSW) register, memory management registers such as
GDTR, LDTR, Task Register (TR) and Interrupt Descriptor Table Register (IDTR).
The 80286 can operate in any one of two memory address modes at any time namely
real address mode or protected virtual address mode (PVAM).
When the 80286 is operating in real address mode, the address unit computes
addresses using a segment base in a segment register and an offset which is in a
register or in the instruction itself as a displacement, just as 8086 does.
The CS, DS, SS and ES registers are used to hold the base address for the segments
currently in use.
The maximum physical address space in real address mode is 1 Mbytes as in 8086.
After reset, the 80286 is configured in real addressing mode and it can be switched to
protected mode, by setting the PE (Protection Enable) bit in the MSW register and
executing a intersegment jump instruction to the start of the main system program.

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Register organization and real &
protected addressing in 80286
When 80286 is operating in PVAM mode, (simply called as
protected mode), the address unit functions as a complete
memory management unit (MMU).
In this mode, the 80286 uses all 24 address lines to access
upto 16 Mbytes of physical memory.
In protected mode, the address unit also provides upto one
gigabyte of virtual memory using descriptor tables.
Virtual memory is managed by the Memory Management Unit
(MMU) in 80286.
When we write an assembly language program, we usually
refer to addresses by name. The addresses with which we
work within a program are called logical addresses or virtual
addresses.
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Register organization and real &
protected addressing in 80286
When a program is assembled or compiled to run on a
system with an MMU such as 80286 in protected mode,
each logical address or virtual address is also
represented by two components.
In a segment oriented system such as 80286, the upper
16-bit component of the logical address is referred to as
a segment selector which is in a segment register and the
lower component of the logical address is referred to as
the offset which is in a register or in the instruction itself
as a displacement
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Virtual to physical address
conversion in 80286 in protected
mode
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Virtual to physical address
conversion in 80286 in protected
mode
A segment descriptor is an 8-byte entry that contains
the physical base address for a segment (base address in
the physical memory such as RAM or ROM in the
system), the privilege level of the segment and some
control bits related to the segment.
By adding the physical base address of the segment
present in the segment descriptor with the offset in the
logical address, the physical memory address is obtained
from where instruction or data is transferred by the
microprocessor
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80286 Segment Descriptor
The base (B23 B0) field represents the 24-bit base address of
a segment in memory and hence a segment can begin at any
location in its 16M bytes of memory.
The limit field (L15-L0) represents the last offset address
found in a segment.
For example if a segment starts at memory location 800000H
and ends at location 800F00H, the base field of that segment
descriptor contains 800000H and the limit field contains
0F00H.
The size of a segment can be between 1 byte and 64K bytes in
80286.

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80286 Segment Descriptor
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Access rights byte in the segment
descriptor (Intel Corp.)

The privilege level of the segment is encoded in the DPL
bits, whether the segment is currently present in physical
memory or not, is encoded in the P bit, whether the
segment is code or data segment or system segment (call
gate, task state segment (TSS), etc.), is encoded in the S
bit and whether the segment is accessed by the CPU or
not, is encoded in the A bit of the segment descriptor.
For code segment or data/stack segment, some more
details are encoded in the bits E, ED/C and W/R bits in
the segment descriptor.

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Access rights byte in the segment
descriptor (Intel Corp.)

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6 Accessing GDT or LDT to select
a segment descriptor (Intel Corp.)
The upper 13-bits in the segment register is known as index
and it selects one of the descriptors from among a maximum
of 8192 descriptors present in either the GDT or LDT.
The TI bit is known as Table Indicator.
If TI = 0 then 80286 refers GDT to select a descriptor and if TI =
1 then 80286 refers LDT to select a descriptor.
The two least significant bits of 80286 are known as
Requestor Privilege Level (RPL) where 00 is the highest
privilege level and 11 is the lowest privilege level.
RPL bits reflect the privilege level of the task requesting
memory access.

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6 Accessing GDT or LDT to select
a segment descriptor (Intel Corp.)

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Privilege levels in protected
mode of operation
Descriptor PL known as DPL, the least PL at which a task may access
that descriptor and the segment associated with that descriptor. It
is determined by bits 6 and 5 in the access rights byte of a
descriptor.
Requestor PL known as RPL, the PL of the original supplier of the
selector in the segment register. RPL is determined by the two least
significant bits of the segment register.
Current PL known as CPL, the PL at which a task is currently
executing which equals the PL of the code segment being executed.
The CPL is stored in the two LSBs of the CS register, except for
conforming code segments.
Effective PL known as EPL is the least privileged of RPL and CPL.
Since maximum PL number represent least previliege level,
EPL = max( RPL, CPL)

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Four level Protection in
80286
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Descriptor cache or
program-invisible registers
Each of the segment register contains a programinvisible register
also known as descriptor register used in the protected mode.
When a new segment number is placed in a segment register, the
microprocessor accesses either LDT or GDT to select a segment
descriptor and loads the segment descriptor copy into the program
invisible register corresponding to that segment register.
It is held there and used to access the memory segment until the
segment number is again changed.
This allows the micro processor to access a memory segment
quickly without referring back to the descriptor table for each
memory access.
The LDTR and TR also have corresponding descriptor cache registers.

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Segment registers and
descriptor registers
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Accessing memory using
GDT and LDT
The GDTR (Global Descriptor Table Register) contain the base address of the global
descriptor table (GDT) and its limit.
The limit of the descriptor table is 16-bits because the maximum table length of the
table is 64K bytes.
When protected mode operation is desired, the base address of the GDT and its limit
are loaded into GDTR.
The location of the local descriptor table (LDT) is selected from the GDT.
There may be many LDTs in the memory at a time depending on the number of tasks
executed by the processor, and each LDT has a corresponding descriptor called LDT
descriptor.
One of the descriptors in GDT is set up to address a particular LDT. To access a
particular LDT, the LDTR (Local Description Table Register) is loaded with a selector.
This selector accesses the GDT to select a LDT descriptor and loads the base address,
limit and access rights of the LDT descriptor into the cache portion of the LDTR.
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Accessing operand from data
segment using GDT
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Accessing operand from
data segment using LDT
In protected mode, the handling of interrupts by the processor is discussed below
The processor can handle a maximum of 256 interrupts. For each interrupt, there is an
interrupt descriptor, which is an 8-byte entry that contains a 16-bit selector to locate the
target code segment which contains the interrupt service routine (ISR) and a 16-bit offset
which is added to the base address of the target code segment to get the starting address
of the ISR.
The interrupt descriptor for each interrupt type, starting from interrupt type 00H are
successively stored in IDT (Interrupt Descriptor Table) present in the memory and the base
address of the IDT is specified by the IDTR (Interrupt Descriptor Table Register).
Whenever an interrupt is received, the processor selects a interrupt descriptor
corresponding to the received interrupt from the IDT and goes to execute the ISR.
Before using protected mode, IDT and the IDTR must be initialized.
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Accessing operand from
data segment using LDT
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Multitasking in 80286
The 80286 is designed for efficient handling of tasks in a multitasking environment.
A task is most often a procedure or application program. In an 80286 system having
multitasking, multiuser OS, the processor switches rapidly between tasks to give an
appearance to the programmer that all tasks are executed simultaneously.
The 80286 supports the task switching operation in hardware.
Each task has a task state segment (TSS) associated with it.
The TSS is used to save the entire state of the machine (all registers content, the
address space and a link to the previous task), and additional information belonging to
the task such as the reason the task is inactive, the time the task spent in running.
The current TSS is identified by the 16-bit register called task register (TR).
The 16-bit TR contains a selector pointing to the TSS descriptor in the GDT that defines
and points the current TSS.
The program-invisible portion of TR is also automatically loaded with the copy of the TSS
descriptor whenever a new value is loaded in TR.

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Addressing modes and new
instructions in 80286
The addressing modes in the 80286 are common to real
mode and protected mode and they are the same as that
of 8086.
The accessing of memory during protected mode
operation by the 80286 using different addressing modes
The 80286 can execute all the instructions of 80186.
In addition, the following new instructions were
introduced in 80286.
CTS, LGDT, SGDT, LIDT, SIDT, LLDT, SLDT, LTR, STR,
LMSW, SMSW, LAR, LSL, ARPL, VERR and VERW.

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Addressing modes and new
instructions in 80286
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Accessing of memory by different addressing
modes in protected mode in 80286
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Flag register in 80286 to
Pentium
The flag register in 8086, 80186 and 80286 is 16 bits and
the flag register present from 80386 to Pentium
processor is 32 bits known as EFLAGS.
The bits that are left empty in the flag register are
reserved for future expansion.
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Flag register in 80286 to
Pentium
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The new bits present in the flag
register from 80286 to Pentium
IOPL (Bits: IOP0 & IOP1):I/O Privilege Level - IOPL is used to
select the privilege level for the I/O devices in the protected
mode operation.
If the current privilege level (CPL) is higher (smaller in
number) than the IOPL, I/O operation is performed without
hindrance.
If the IOPL is lower than the CPL, an interrupt occurs, causing
execution to suspend.
Note that an IOPL of 00 is having higher privilege level and
IOPL of 11 has the least privilege level.
For example, if the CPL is 00H and IOPL is 01H then I/O
operation is performed without hindrance.

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The new bits present in the flag
register from 80286 to Pentium
NT (Nested Task) The nested task flag indicates that the
current task is nested within another task in protected
mode operation. This flag is set when the task is nested
by software.
RF (Resume Flag) The resume flag is used with
debugging to control the resumption of execution after
the next instruction.

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The new bits present in the flag
register from 80286 to Pentium
VM (Virtual mode) If VM is set, the microprocessor enters
the virtual 8086 mode within the protected mode.
This flag has to be set only when the processor is in protected
mode using IRET instruction or any task switch operation.
The VM bit selects virtual mode operation in a protected
mode system.
A virtual mode system allows multiple DOS (Disk Operating
System) memory partitions that are 1 Mbytes in length to
coexist in the memory.
This allows the system program to execute multiple DOS
programs in the computer.

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The new bits present in the flag
register from 80286 to Pentium
AC (Alignment Check) The AC flag is set if a word or
double word is accessed from a non-word or non- double
word boundary.
VIF (Virtual Interrupt Flag)- The VIF is a copy of interrupt
flag bit available to the Pentium.
VIP (Virtual Interrupt Pending)- VIP provides information
about the virtual mode interrupt for the Pentium.
This is used in a multitasking environment to provide the
operating system with virtual interrupt flags and
interrupt pending information.

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The new bits present in the flag
register from 80286 to Pentium
ID (Identification) The ID flag indicates that the
Pentium supports the CPUID instruction.
The CPUID instruction provides the system with
information about the Pentium such as its version
number and manufacturer.
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